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On-Demand

    Functional Verification On-Demand Training Library
    

    

    

    This library contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies.
    

    Learn how to use ModelSim/Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.
    
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HDL & Other Languages
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Questa & ModelSim

    

    
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    Learning Paths
    

    

    

    Learning paths let you focus on developing the skills you need most.
    


    


    

    

    

    

    


    

8 Chapters

    

    

    
Learning Path

    SystemVerilog Fundamentals
    

    In this learning path you will learn SystemVerilog fundamentals such as blocks, data types, and operators.
    

    

    

    


    
Preview Chapter

    SystemVerilog Verification Introduction
    

    
    

    

    

    


    



    

    

    

    

    


    

4 Chapters

    

    

    
Learning Path

    Questa Sim Coverage Acceleration Apps with inFact
    

    In this learning path you will learn to use Questa inFact PSS to generate portable stimulus and achieve coverage faster than other stimulus generation methods.
    

    

    


    



    

    

    

    

    


    

1 Chapter

    

    

    
Learning Path

    MLC Overview and Functional Verification Curriculum
    

    Learn how to navigate the Mentor Learning Center and view curriculum maps for Functional verification Library.
    

    

    

    


    
Preview Chapter

    Mentor Learning Center Overivew
    

    
    

    

    

    


    



    

    

    

    

    


    

3 Chapters

    

    

    
Learning Path

    SystemVerilog OOP and IPC
    

    In this learning path you will learn SystemVerilog Object Oriented Programming and Inter-Process Communication.
    

    

    

    


    
Preview Chapter

    SystemVerilog Introduction to Classes
    

    
    

    

    

    


    



    

    

    

    

    


    

6 Chapters

    

    

    
Learning Path

    ModelSim / Questa Core HDL Simulation
    

    Learn how to use ModelSim / Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.
    

    

    

    


    
Preview Chapter

    ModelSim/Questa: Simulation in the Digital Design Flow
    

    
    

    

    

    


    



    

    

    

    

    


    

6 Chapters

    

    

    
Learning Path

    HDS: Basic Operation
    

    This learning path covers the core operations of HDL Designer (HDS), use of the Block Diagram, and State Machine editors and how to control simulations from HDS
    

    

    

    


    
Preview Chapter

    HDS: Introduction to Design Explorer in Logical Object  Mode
    

    
    

    

    

    


    


    




    


    

    

    


    

    

    

    
18
Learning
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92
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912
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57
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    Receive unlimited access to all new content added during your active subscription.
    

    During your subscription period, you will automatically receive access to all new content added to the library, including training on new product releases and technology updates to maximize your proficiency.
    

    

    

    



    

    

    

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    Functional Verification On-Demand Training Library
    


    

    

    

    

    SystemVerilog Fundamentals 8 Chapters
    

    In this learning path you will learn SystemVerilog fundamentals such as blocks, data types, and operators.
    

    

    

    1 SystemVerilog Concepts 12 Topics
    

      

    1. SystemVerilog Verification Introduction
      2. 

    2. SystemVerilog Random Verification
      3. 

    3. SystemVerilog Coverage
      4. 

    4. SystemVerilog Levels of Abstraction
      5. 

    5. Knowledge Check 1: SystemVerilog Concepts
      6. 

    6. SystemVerilog Compiler Directives
      7. 

    7. SystemVerilog Time and Delays
      8. 

    8. SystemVerilog System Tasks and Functions
      9. 

    9. SystemVerilog Testbench Organization
      10. 

    10. Knowledge Check 2: SystemVerilog Concepts
      11. 

    11. Lab: Simulate and Debug a 1-bit Adder
      12. 

    12. Assessment: SystemVerilog Concepts
      13. 

    

    

    

    2 SystemVerilog Integral Data Types 16 Topics
    

      

    1. SystemVerilog Syntax
      2. 

    2. SystemVerilog Literals
      3. 

    3. SystemVerilog Data Types and Value Sets
      4. 

    4. SystemVerilog Vectors
      5. 

    5. Knowledge Check 1: SystemVerilog Integral Data Types
      6. 

    6. SystemVerilog Enumerated Types
      7. 

    7. SystemVerilog User Defined Types
      8. 

    8. SystemVerilog Casting
      9. 

    9. Knowledge Check 2: SystemVerilog Integral Data Types
      10. 

    10. SystemVerilog Hierarchical References
      11. 

    11. SystemVerilog Port Declaration
      12. 

    12. SystemVerilog Port Connections
      13. 

    13. SystemVerilog Parameters and Constants
      14. 

    14. Knowledge Check 3: SystemVerilog Integral Data Types
      15. 

    15. Lab: Using 4-State and 2-State Types
      16. 

    16. Assessment: SystemVerilog Integral Data Types
      17. 

    

    

    

    3 SystemVerilog Procedural Blocks and Routines 12 Topics
    

      

    1. SystemVerilog Event Simulation
      2. 

    2. SystemVerilog Initial and Always Blocks
      3. 

    3. SystemVerilog Blocking and Non-blocking Assignment Statements
      4. 

    4. SystemVerilog Continuous Assignment Statements
      5. 

    5. Knowledge Check 1: SystemVerilog Procedural Blocks and Routines
      6. 

    6. SystemVerilog Tasks and Functions
      7. 

    7. SystemVerilog Routine Arguments
      8. 

    8. SystemVerilog Routine Storage
      9. 

    9. SystemVerilog Ref Arguments and Defaults
      10. 

    10. Knowledge Check 2: SystemVerilog Procedural Blocks and Routines
      11. 

    11. Lab: Model and Verify a Johnson Counter
      12. 

    12. Assessment: SystemVerilog Procedural Blocks and Routines
      13. 

    

    

    

    4 SystemVerilog Programming Statements 9 Topics
    

      

    1. SystemVerilog If and Assert Statements
      2. 

    2. SystemVerilog Case Statements
      3. 

    3. Knowledge Check 1: SystemVerilog Programming Statements
      4. 

    4. SystemVerilog Forever, Repeat, and While Loops
      5. 

    5. SystemVerilog For-loop and Foreach-loop
      6. 

    6. SystemVerilog Labels and the Disable, Continue, and Break Statements
      7. 

    7. Knowledge Check 2: SystemVerilog Programming Statements
      8. 

    8. Lab: Model and Verify a BCD Encoder
      9. 

    9. Assessment: SystemVerilog Programming Statements
      10. 

    

    

    

    5 SystemVerilog Operators 15 Topics
    

      

    1. SystemVerilog Operators Introduction
      2. 

    2. SystemVerilog Bitwise and Unary-Reduction Operators
      3. 

    3. SystemVerilog Logical and Comparison Operators
      4. 

    4. SystemVerilog Equality Operators
      5. 

    5. SystemVerilog Inside Operator
      6. 

    6. Knowledge Check 1: SystemVerilog Operators
      7. 

    7. SystemVerilog Shift and Concatenate Operators
      8. 

    8. SystemVerilog Conditional Operator
      9. 

    9. SystemVerilog Arithmetic Operators
      10. 

    10. SystemVerilog Streaming Operators
      11. 

    11. SystemVerilog Assignment Operators
      12. 

    12. SystemVerilog Operation Size
      13. 

    13. Knowledge Check 2: SystemVerilog Operators
      14. 

    14. Lab: Model and Verify an ALU
      15. 

    15. Assessment: SystemVerilog Operators
      16. 

    

    

    
Discover

    6 SystemVerilog Arrays, Structures, and Packages 18 Topics
    

      

    1. SystemVerilog - Vectors and Arrays
      2. 

    2. SystemVerilog Array - Assignment and Comparison
      3. 

    3. SystemVerilog - Array Literals
      4. 

    4. Knowledge Check 1: SystemVerilog Arrays, Structures, and Packages
      5. 

    5. SystemVerilog - Dynamic Arrays
      6. 

    6. SystemVerilog - Strings
      7. 

    7. SystemVerilog - Queues
      8. 

    8. Knowledge Check 2: SystemVerilog Arrays, Structures, and Packages
      9. 

    9. SystemVerilog - Associative Arrays
      10. 

    10. SystemVerilog - Array Methods
      11. 

    11. SystemVerilog - Advanced Array Methods
      12. 

    12. Knowledge Check 3: SystemVerilog Arrays, Structures, and Packages
      13. 

    13. SystemVerilog - Structures
      14. 

    14. SystemVerilog - Packages
      15. 

    15. SystemVerilog - Package Import
      16. 

    16. Knowledge Check 4: SystemVerilog Arrays, Structures, and Packages
      17. 

    17. Lab: SystemVerilog Arrays, Structures, and Packages
      18. 

    18. Assessment: SystemVerilog Arrays, Structures, and Packages
      19. 

    

    

    

    7 SystemVerilog Interfaces 9 Topics
    

      

    1. SystemVerilog - Ports and Interfaces
      2. 

    2. SystemVerilog Interface - Signals, Methods and Ports
      3. 

    3. SystemVerilog - Modports
      4. 

    4. Knowledge Check 1: SystemVerilog Interfaces
      5. 

    5. SystemVerilog - Parameterized Interfaces
      6. 

    6. SystemVerilog - Connecting with Interfaces
      7. 

    7. Knowledge Check 2: SystemVerilog Interfaces
      8. 

    8. Lab: Create an Inter-processor Interface
      9. 

    9. Assessment: SystemVerilog Interfaces
      10. 

    

    

    

    8 SystemVerilog Verification Constructs 10 Topics
    

      

    1. SystemVerilog - Final Block
      2. 

    2. SystemVerilog - Fork-Join Introduction
      3. 

    3. SystemVerilog - Fork-Join Flavors
      4. 

    4. Knowledge Check 1: SystemVerilog Verification Constructs
      5. 

    5. SystemVerilog - Force and Release
      6. 

    6. SystemVerilog - Reading Memory Files
      7. 

    7. SystemVerilog - File I/O
      8. 

    8. Knowledge Check 2: SystemVerilog Verification Constructs
      9. 

    9. Lab: Verify with Testbench Interfaces
      10. 

    10. Assessment: SystemVerilog Verification Constructs
      11. 

    

    

    

    

    

    Questa Sim Coverage Acceleration Apps with inFact 4 Chapters
    

    In this learning path you will learn to use Questa inFact PSS to generate portable stimulus and achieve coverage faster than other stimulus generation methods.
    

    

    
Discover

    1 Stimulus Optimization with inFact 2 Topics
    

      

    1. Reference: Stimulus Optimization with inFact
      2. 

    2. Lab: Stimulus Optimization with inFact
      3. 

    

    

    
Discover

    2 Regression Optimization with inFact 2 Topics
    

      

    1. Reference: Regression Optimization with inFact
      2. 

    2. Lab: Regression Optimization with inFact
      3. 

    

    

    
Discover

    3 Coverage Goal Optimization with inFact 2 Topics
    

      

    1. Reference: Coverage Goal Optimization with inFact
      2. 

    2. Lab: Coverage Goal Optimization with inFact
      3. 

    

    

    
Discover

    4 Scenario Generation Optimization with inFact and PSS 2 Topics
    

      

    1. Reference: Scenario Generation Optimization with inFact and PSS
      2. 

    2. Lab: Scenario Generation Optimization with inFact and PSS
      3. 

    

    

    

    

    

    MLC Overview and Functional Verification Curriculum 1 Chapter
    

    Learn how to navigate the Mentor Learning Center and view curriculum maps for Functional verification Library.
    

    

    

    1 Mentor Learning Center Overview and Functional Verification Curriculum 6 Topics
    

      

    1. Mentor Learning Center Overivew
      2. 

    2. Video, Quiz, and Lab Times
      3. 

    3. ModelSim/Questa Curriculum Map
      4. 

    4. Languages Curriculum Map
      5. 

    5. HDL Designer Series Curriculum Map
      6. 

    6. Formal Verification Curriculum Map
      7. 

    

    

    

    

    

    SystemVerilog OOP and IPC 3 Chapters
    

    In this learning path you will learn SystemVerilog Object Oriented Programming and Inter-Process Communication.
    

    

    
Discover

    1 SystemVerilog Basic OOP 17 Topics
    

      

    1. SystemVerilog Introduction to Object Oriented Programming
      2. 

    2. SystemVerilog Introduction to Classes
      3. 

    3. SystemVerilog Questa Sim OOP Debug
      4. 

    4. SystemVerilog Constructors
      5. 

    5. Knowledge Check 1: SystemVerilog Basic OOP
      6. 

    6. SystemVerilog Handles and Objects 1
      7. 

    7. SystemVerilog Handles and Objects 2
      8. 

    8. SystemVerilog Shallow Object Copy
      9. 

    9. SystemVerilog Deep Object Copy
      10. 

    10. SystemVerilog Cloning Objects
      11. 

    11. Knowledge Check 2: SystemVerilog Basic OOP
      12. 

    12. SystemVerilog Class Declaration Details
      13. 

    13. SystemVerilog Static Properties and Methods
      14. 

    14. SystemVerilog Virtual Interfaces
      15. 

    15. Knowledge Check 3: SystemVerilog Basic OOP
      16. 

    16. Lab: SystemVerilog Basic OOP
      17. 

    17. Assessment: SystemVerilog Basic OOP
      18. 

    

    

    

    2 SystemVerilog Advanced OOP 15 Topics
    

      

    1. SystemVerilog Class Extension
      2. 

    2. SystemVerilog Advanced OOP Terminology
      3. 

    3. SystemVerilog Transaction Generator
      4. 

    4. Knowledge Check 1: SystemVerilog Advanced OOP
      5. 

    5. SystemVerilog Handles and Objects 3
      6. 

    6. SystemVerilog Virtual Methods
      7. 

    7. SystemVerilog Virtual Method Prototype
      8. 

    8. Knowledge Check 2: SystemVerilog Advanced OOP
      9. 

    9. SystemVerilog Generator and Virtual Methods
      10. 

    10. SystemVerilog Advanced Constructors
      11. 

    11. SystemVerilog Parameterized Classes
      12. 

    12. SystemVerilog Class Member Visibility
      13. 

    13. Knowledge Check 3: SystemVerilog Advanced OOP
      14. 

    14. Lab: SystemVerilog Advanced OOP
      15. 

    15. Assessment: SystemVerilog Advanced OOP
      16. 

    

    

    

    3 SystemVerilog Interprocess Communication 9 Topics
    

      

    1. SystemVerilog Introduction to Interprocess Communication
      2. 

    2. SystemVerilog Fork-Join
      3. 

    3. SystemVerilog Fork-Join_none
      4. 

    4. SystemVerilog Fork-Join_any
      5. 

    5. Knowledge Check 1: SystemVerilog Interprocess Communication
      6. 

    6. SystemVerilog Disable Threads
      7. 

    7. SystemVerilog Spawning Threads in a Loop
      8. 

    8. Knowledge Check 2: SystemVerilog Interprocess Communication
      9. 

    9. Assessment: SystemVerilog Interprocess Communication
      10. 

    

    

    

    

    

    ModelSim / Questa Core HDL Simulation 6 Chapters
    

    Learn how to use ModelSim / Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.
    

    

    
Discover

    1 ModelSim/Questa HDL Simulation Learning Path Overview 1 Topic
    

      

    1. Learning Path Overview
      2. 

    

    

    
Discover

    2 ModelSim/Questa Introduction to Simulation 11 Topics
    

      

    1. ModelSim/Questa: Simulation in the Digital Design Flow
      2. 

    2. ModelSim/Questa: Simulation Process
      3. 

    3. Knowledge Check 1: ModelSim/Questa Introduction to Simulation
      4. 

    4. ModelSim/Questa: Overview of Features and Supported Industry Standards
      5. 

    5. ModelSim/Questa: Modes of Operation
      6. 

    6. ModelSim/Questa: Overview of Debugging Capabilities
      7. 

    7. Knowledge Check 2: ModelSim/Questa Introduction to Simulation
      8. 

    8. ModelSim/Questa: Getting Help
      9. 

    9. Knowledge Check 3: ModelSim/Questa Introduction to Simulation
      10. 

    10. Lab: ModelSim/Questa Documentation and Help
      11. 

    11. Assessment: ModelSim/Questa Introduction to Simulation
      12. 

    

    

    

    3 ModelSim/Questa Basic Simulation Using Commands and Do Files 11 Topics
    

      

    1. ModelSim/Questa: Command Line Overview
      2. 

    2. ModelSim/Questa: Libraries and Design Units
      3. 

    3. Knowledge Check 1: ModelSim/Questa Basic Simulation using Commands and Do Files
      4. 

    4. ModelSim/Questa: Compilation and Optimization Commands
      5. 

    5. ModelSim/Questa: Basic Simulation Commands
      6. 

    6. Knowledge Check 2: ModelSim/Questa Basic Simulation using Commands and Do Files
      7. 

    7. ModelSim/Questa: Simple Stimulus using Simulator
      8. 

    8. ModelSim/Questa: Saving Session for Simple Do Files
      9. 

    9. Knowledge Check 3: ModelSim/Questa Basic Simulation using Commands and Do Files
      10. 

    10. Lab: ModelSim/Questa Command Line Simulation
      11. 

    11. Assessment: ModelSim/Questa Basic Simulation using Commands and Do Files
      12. 

    

    

    

    4 ModelSim/Questa Graphical User Interface 26 Topics
    

      

    1. ModelSim/Questa: Quick Overview of GUI Operation
      2. 

    2. ModelSim/Questa: Window Movement and Topology
      3. 

    3. Knowledge Check 1: ModelSim/Questa - Graphical User Interface
      4. 

    4. ModelSim/Questa: Setting GUI Preferences
      5. 

    5. ModelSim/Questa: Searching and Sorting in the GUI
      6. 

    6. Knowledge Check 2: ModelSim/Questa - Graphical User Interface
      7. 

    7. ModelSim/Questa: Structure Window
      8. 

    8. ModelSim/Questa: Project Window
      9. 

    9. ModelSim/Questa: Memory Windows
      10. 

    10. ModelSim/Questa: Message Viewer Window
      11. 

    11. Knowledge Check 3: ModelSim/Questa - Graphical User Interface
      12. 

    12. ModelSim/Questa: Source Window
      13. 

    13. ModelSim/Questa: Objects Window
      14. 

    14. ModelSim/Questa: Processes and Locals Windows
      15. 

    15. Knowledge Check 4: ModelSim/Questa - Graphical User Interface
      16. 

    16. ModelSim/Questa: Dataflow Window
      17. 

    17. ModelSim/Questa: Schematic Window
      18. 

    18. ModelSim/Questa: List Window
      19. 

    19. Knowledge Check 5: ModelSim/Questa - Graphical User Interface
      20. 

    20. ModelSim/Questa: Watch Window
      21. 

    21. ModelSim/Questa: Wave Window
      22. 

    22. ModelSim/Questa: Wave Window Debugging Capabilities
      23. 

    23. ModelSim/Questa: Introduction to FSM Windows
      24. 

    24. Knowledge Check 6: ModelSim/Questa - Graphical User Interface
      25. 

    25. Lab: ModelSim/Questa Introduction to the GUI
      26. 

    26. Assessment: ModelSim/Questa - Graphical User Interface
      27. 

    

    

    

    5 ModelSim/Questa Basic Simulation Using the GUI 17 Topics
    

      

    1. ModelSim/Questa: Advantages of Running Simulations in the GUI
      2. 

    2. ModelSim/Questa: Creating Libraries in the GUI
      3. 

    3. Knowledge Check 1: ModelSim/Questa Basic Simulation using the GUI
      4. 

    4. ModelSim/Questa: Compiling using the GUI
      5. 

    5. ModelSim/Questa: Simulating using the GUI
      6. 

    6. ModelSim/Questa: Running Simulation using the GUI
      7. 

    7. ModelSim/Questa: Using Breakpoints
      8. 

    8. Knowledge Check 2: ModelSim/Questa Basic Simulation using the GUI
      9. 

    9. ModelSim/Questa: What is a Project?
      10. 

    10. ModelSim/Questa: Creating a Project in the GUI
      11. 

    11. ModelSim/Questa: Setting Project Properties
      12. 

    12. Knowledge Check 3: ModelSim/Questa Basic Simulation using the GUI
      13. 

    13. ModelSim/Questa: Using a Project in the GUI
      14. 

    14. ModelSim/Questa: Using the Project Command
      15. 

    15. Knowledge Check 4: ModelSim/Questa Basic Simulation using the GUI
      16. 

    16. Lab: ModelSim/Questa Running Simulations in the GUI
      17. 

    17. Assessment: ModelSim/Questa Basic Simulation using the GUI
      18. 

    

    

    

    6 ModelSim/Questa Mixed-HDL Designs 8 Topics
    

      

    1. ModelSim/Questa: Mixed-HDL Design Considerations
      2. 

    2. ModelSim/Questa: Verilog inside VHDL
      3. 

    3. ModelSim/Questa: VHDL inside Verilog
      4. 

    4. Knowledge Check 1: ModelSim/Questa Mixed-HDL Designs
      5. 

    5. ModelSim/Questa: Accessing Objects in a Mixed Design
      6. 

    6. Knowledge Check 2: ModelSim/Questa Mixed-HDL Designs
      7. 

    7. Lab: ModelSim/Questa Mixed HDL Design
      8. 

    8. Assessment: ModelSim/Questa Mixed-HDL Designs
      9. 

    

    

    

    

    

    HDS: Basic Operation 6 Chapters
    

    This learning path covers the core operations of HDL Designer (HDS), use of the Block Diagram, and State Machine editors and how to control simulations from HDS
    

    

    

    1 HDS: HDL Designer Basics 23 Topics
    

      

    1. HDS: What is HDL Designer?
      2. 

    2. HDS: Getting Help
      3. 

    3. Knowledge Check 1: HDS - Basics
      4. 

    4. HDS: Design Manager Basics
      5. 

    5. HDS: Initial Configuration of HDS
      6. 

    6. HDS: Project Manager Contents
      7. 

    7. HDS: Creating and Opening Projects in HDS
      8. 

    8. Knowledge Check 2: HDS - Basics
      9. 

    9. HDS: Creating Libraries and What They Contain
      10. 

    10. Lab: HDS Project and Library
      11. 

    11. HDS: Introduction to Design Explorer in Design Unit mode
      12. 

    12. HDS: Using the Hierarchy Pane in Design Explorer
      13. 

    13. Knowledge Check 3: HDS - Basics
      14. 

    14. HDS: Copying Design Units and Views in the Design Explorer
      15. 

    15. HDS: Introduction to Design Explorer in File Browser Mode
      16. 

    16. HDS: Introduction to Design Explorer in Logical Object  Mode
      17. 

    17. Knowledge Check 4: HDS - Basics
      18. 

    18. HDS: How to Use the Design Explorer Side Data Windows
      19. 

    19. HDS: How to Use the Design Explorer Downstream Windows
      20. 

    20. HDS: How to Use the Design Explorer Task and Template Windows
      21. 

    21. Knowledge Check 5: HDS - Basics
      22. 

    22. Lab: HDS Introduction to Design Explorer
      23. 

    23. Assessment: HDS Basics
      24. 

    

    

    
Discover

    2 HDS: Design Entry Common Features 15 Topics
    

      

    1. HDS: Opening New or Existing Design Units
      2. 

    2. HDS: Bottom Up Design Flow
      3. 

    3. HDS: Top Down Design Flow
      4. 

    4. HDS: How to Save the Design
      5. 

    5. Knowledge Check 1: HDS Common Features
      6. 

    6. Lab: HDS Opening and Closing Designs
      7. 

    7. HDS: Adding Comments to Design Entry Tools
      8. 

    8. HDS: Defining the Page Setup for Viewing and Printing
      9. 

    9. HDS: Setting Package Preferences
      10. 

    10. HDS: Setting Preferences for the Design Tools
      11. 

    11. HDS: Using the Diagram Browser
      12. 

    12. HDS: How to Generate HDL Code from Graphics
      13. 

    13. Knowledge Check 2: HDS Common Features
      14. 

    14. Lab: HDS Preferences
      15. 

    15. Assessment: HDS Common Features
      16. 

    

    

    

    3 HDS: Block Diagrams 24 Topics
    

      

    1. HDS: Definition and Use of Block Diagrams
      2. 

    2. HDS: Adding Blocks and Components
      3. 

    3. HDS: Adding ModuleWare
      4. 

    4. Lab: HDS Adding Blocks and Components
      5. 

    5. HDS: Adding Connections to Block Diagrams
      6. 

    6. HDS: Connecting Blocks and Components
      7. 

    7. HDS: Adding Ports to Block Diagrams
      8. 

    8. HDS: Auto and Interactive Routing
      9. 

    9. Knowledge Check 1: HDS Block Diagram
      10. 

    10. HDS: Setting Block and Component Properties
      11. 

    11. HDS: Promoting Blocks to Components
      12. 

    12. HDS: Setting Signal and Port Properties
      13. 

    13. HDS: User Declarations and Visibility
      14. 

    14. Knowledge Check 2: HDS Block Diagram
      15. 

    15. Lab: HDS Connecting Up Block Diagrams
      16. 

    16. HDS: Navigating Through Block Diagram Hierarchy
      17. 

    17. HDS: Reconciling Interfaces
      18. 

    18. HDS: Highlighting Nets Through Hierarchy
      19. 

    19. HDS: Changing Hierarchical Nets
      20. 

    20. HDS: Adding and Removing Hierarchy from Block Diagrams
      21. 

    21. HDS: Looking at Block Diagrams as IBDs
      22. 

    22. HDS Block Diagram Knowledge Check 3
      23. 

    23. Lab: HDS: Manipulating Block Diagrams
      24. 

    24. Assessment: HDS Block Diagram
      25. 

    

    

    

    4 HDS: State Machine Creation 17 Topics
    

      

    1. HDS: State Machine Objects and How to Add Them
      2. 

    2. HDS: Adding and Removing Hierarchy to the State Diagram
      3. 

    3. HDS: Using Wait States
      4. 

    4. Knowledge Check 1: HDS State Machine Creation
      5. 

    5. HDS: Making State Assignments
      6. 

    6. Lab: HDS: Adding Objects to State Diagrams
      7. 

    7. HDS: Transition Conditions and Assignments
      8. 

    8. HDS: Output Assignment Priority
      9. 

    9. HDS: Implementing Moore and/or Mealy State Machines
      10. 

    10. HDS: Defining Clock, Reset and Enable
      11. 

    11. Knowledge Check 2: HDS State Machine Creation
      12. 

    12. Lab: HDS: Adding Transitions to State Diagrams
      13. 

    13. HDS: Using Concurrent State Machines
      14. 

    14. HDS: The Expression Builder
      15. 

    15. Knowledge Check 3: HDS State Machine Creation
      16. 

    16. Lab: HDS: Concurrent State Diagrams
      17. 

    17. Assessment: HDS: State Machine Creation
      18. 

    

    

    

    5 HDS: State Machine Code Generation 12 Topics
    

      

    1. HDS: Common State Machine HDL Styles
      2. 

    2. HDS: Using Output Default Values
      3. 

    3. HDS: Timing Differences between Output Signal Types Part 1
      4. 

    4. HDS: Timing Differences between Output Signal Types Part 2
      5. 

    5. HDS: Adding Declarations and Statements to the State Machine Code
      6. 

    6. Knowledge Check 1: HDS: State Machine Code Generation
      7. 

    7. HDS: Defining the Format of State Machine HDL
      8. 

    8. HDS: Defining State Encoding for Synthesis
      9. 

    9. HDS: Analyzing Signals Table
      10. 

    10. Knowledge Check 2: HDS: State Machine Code Generation
      11. 

    11. Lab: HDS Generating State Machine HDL Code
      12. 

    12. Assessment: HDS State Machine Code Generation
      13. 

    

    

    

    6 HDS: Simulating and Debugging Designs Within HDS 17 Topics
    

      

    1. HDS: Creating a Top Level Testbench in HDL Designer
      2. 

    2. HDS: Describing Tester Operation in HDL Designer
      3. 

    3. Knowledge Check 1: HDS: Simulating and Debugging Designs Within HDS
      4. 

    4. Lab: HDS: Creation of a Testbench
      5. 

    5. HDS: Setting Up the Chosen Simulator
      6. 

    6. HDS: Starting the Simulation
      7. 

    7. HDS: Solving Compile and Elaboration Errors
      8. 

    8. Knowledge Check 2: HDS: Simulating and Debugging Designs Within HDS
      9. 

    9. Lab: HDS: Compiling and Entering the Simulator
      10. 

    10. HDS: Running the Simulation from HDS Windows
      11. 

    11. HDS: Setting Breakpoints from HDS Windows
      12. 

    12. HDS: Animating HDS Windows During Simulation
      13. 

    13. HDS: Reviewing Animation History
      14. 

    14. HDS: How to Enable Code Coverage Collection in Simulator
      15. 

    15. Knowledge Check 3: HDS: Simulating and Debugging Designs Within HDS
      16. 

    16. Lab: HDS: Simulation Control and Animation
      17. 

    17. Assessment: HDS: Simulating and Debugging Designs Within HDS
      18. 

    

    

    

    

    

    SystemVerilog Randomization and Functional Coverage 2 Chapters
    

    In this learning path you will learn about SystemVerilog Constrained Random Generation and Functional Coverage.
    

    

    
Discover

    1 SystemVerilog Randomization 19 Topics
    

      

    1. SystemVerilog Class-Based Randomization
      2. 

    2. SystemVerilog Randomization Example
      3. 

    3. SystemVerilog Constraint Solver
      4. 

    4. SystemVerilog Membership, Distribution, and Unique Constraints
      5. 

    5. SystemVerilog Implication Constraint
      6. 

    6. Knowledge Check 1: SystemVerilog Randomization
      7. 

    7. SystemVerilog Randomizing Arrays
      8. 

    8. SystemVerilog Randomizing Aggregate Types
      9. 

    9. SystemVerilog Random Distribution and Probability
      10. 

    10. SystemVerilog Constraint Inheritance and In-Line Constraints
      11. 

    11. SystemVerilog Soft Constraints
      12. 

    12. Knowledge Check 2: SystemVerilog Randomization
      13. 

    13. SystemVerilog Randomization Setup and Cleanup
      14. 

    14. SystemVerilog Random Cyclic Variables
      15. 

    15. SystemVerilog Disabling Randomization
      16. 

    16. SystemVerilog Randomization Issues and Alternatives
      17. 

    17. Knowledge Check 3: SystemVerilog Randomization
      18. 

    18. Lab: SystemVerilog Randomization
      19. 

    19. Assessment: SystemVerilog Randomization
      20. 

    

    

    

    2 SystemVerilog Functional Coverage 17 Topics
    

      

    1. SystemVerilog Coverage Comparison
      2. 

    2. SystemVerilog Functional Coverage Strategies
      3. 

    3. SystemVerilog Functional Coverage Flow
      4. 

    4. Knowledge Check 1: SystemVerilog Functional Coverage
      5. 

    5. SystemVerilog Covergroup Definition
      6. 

    6. SystemVerilog Sampling and Conditional Coverage
      7. 

    7. SystemVerilog Coverpoint Bins
      8. 

    8. SystemVerilog Special Coverage Bins
      9. 

    9. Knowledge Check 2: SystemVerilog Functional Coverage
      10. 

    10. SystemVerilog Cross Coverage
      11. 

    11. SystemVerilog Generic Covergroups
      12. 

    12. SystemVerilog Coverage Options
      13. 

    13. SystemVerilog Coverage Methods
      14. 

    14. SystemVerilog Transition Coverage
      15. 

    15. Knowledge Check 3: SystemVerilog Functional Coverage
      16. 

    16. Lab: SystemVerilog Functional Coverage
      17. 

    17. Assessment: SystemVerilog Functional Coverage
      18. 

    

    

    

    

    

    ModelSim / Questa Core Advanced Topics 5 Chapters
    

    This learning path enables you to extend your knowledge of ModleSim/QuestaSim functionality and to efficiently analyze and debug HDL code.
    

    

    
Discover

    1 ModelSim/Questa Tcl/TK Overview 10 Topics
    

      

    1. ModelSim / Questa: Why Use Tcl/Tk?
      2. 

    2. ModelSim / Questa: Tcl Overview
      3. 

    3. ModelSim / Questa: Tcl Syntax
      4. 

    4. ModelSim / Questa: Using vsim Commands in Tcl Scripts
      5. 

    5. ModelSim / Questa: Simple Simulation Scripts
      6. 

    6. Knowledge Check 1: ModelSim/Questa - Tcl/Tk Overview
      7. 

    7. ModelSim / Questa: Tk Widgets and Custom GUI Buttons
      8. 

    8. Knowledge Check 2: ModelSim/Questa - Tcl/Tk Overview
      9. 

    9. Lab: ModelSim/Questa - Using Scripts and Tk Widgets  in Simulation
      10. 

    10. Assessment: ModelSim/Questa - TCL/TK Overview
      11. 

    

    

    

    2 ModelSim/Questa Code Coverage 15 Topics
    

      

    1. ModelSim / Questa: Purpose and Benefits of Code Coverage
      2. 

    2. ModelSim / Questa: Types of Code Coverage
      3. 

    3. Knowledge Check 1: ModelSim/Questa - Code Coverage
      4. 

    4. ModelSim / Questa: Invoking Code Coverage
      5. 

    5. ModelSim / Questa: Code Coverage Analysis Windows
      6. 

    6. Knowledge Check 2: ModelSim/Questa - Code Coverage
      7. 

    7. ModelSim / Questa: Managing Coverage Exclusions
      8. 

    8. ModelSim / Questasim: Reporting Coverage
      9. 

    9. Knowledge Check 3: ModelSim/Questa - Code Coverage
      10. 

    10. Lab: ModelSim/Questa - Performing Code Coverage
      11. 

    11. Modelsim / QuestaSim: Saving Coverage Data (UCDB)
      12. 

    12. ModelSim / Questa: Managing Coverage Data
      13. 

    13. Knowledge Check 4: ModelSim/Questa Code Coverage
      14. 

    14. Lab: ModelSim/Questa - Analyzing Code Coverage Results
      15. 

    15. Assessment: ModelSim/Questa - Code Coverage
      16. 

    

    

    

    3 ModelSim/Questa Language Support and Gate Level Simulations 13 Topics
    

      

    1. ModelSim / Questa: SDF Annotation, VHDL and VHDL VITAL
      2. 

    2. ModelSim / Questa: VHDL Coding for Performance
      3. 

    3. Knowledge Check 1: ModelSim/Questa - Language Support
      4. 

    4. ModelSim / Questa: Verilog / SystemVerilog Version Support
      5. 

    5. ModelSim / Questa: How to Compile SV Files
      6. 

    6. ModelSim / Questa: Verilog Coding for Maximum Performance
      7. 

    7. Knowledge Check 2: ModelSim/Questa - Language Support
      8. 

    8. ModelSim / Questa: Verilog Delay Modes for Gate Level Simulations
      9. 

    9. ModelSim / Questa: Verilog SDF Timing Annotation
      10. 

    10. ModelSim / Questa: Verilog Gate Level Optimizations
      11. 

    11. Knowledge Check 3: ModelSim/Questa - Language Support
      12. 

    12. Lab: ModelSim/Questa - Gate Level Simulation
      13. 

    13. Assessment: ModelSim/Questa - Gate Level
      14. 

    

    

    

    4 ModelSim/Questa Finite State Machine Viewer 6 Topics
    

      

    1. ModelSim/Questa: FSM Recognition
      2. 

    2. Knowledge Check 1: ModelSim/Questa FSM
      3. 

    3. ModelSim/Questa: Viewing FSM in GUI
      4. 

    4. Knowledge Check 2: ModelSim/Questa FSM
      5. 

    5. Lab: ModelSim/Questa Finite State Machine
      6. 

    6. Assessment: ModelSim/Questa FSM
      7. 

    

    

    

    5 ModelSim/Questa Selected Debugging Topics 18 Topics
    

      

    1. ModelSim / Questa: Why Debug is Needed?
      2. 

    2. ModelSim / Questa: Checkpoint and Restore
      3. 

    3. ModelSim / Questa: Contention and Float Checking
      4. 

    4. ModelSim / Questa: Toggle and Stability Checking
      5. 

    5. ModelSim / Questa: Iteration Violations
      6. 

    6. Knowledge Check 1: ModelSim/Questa - Debugging
      7. 

    7. ModelSim / Questa: Post Simulation Analysis
      8. 

    8. ModelSim / Questa: IP Integrity
      9. 

    9. Lab: ModelSim / Quest - Iteration Limit
      10. 

    10. ModelSim / Questa: Hyperlinked Navigation
      11. 

    11. ModelSim / Questa: Tracing Readers and Drivers
      12. 

    12. Knowledge Check 2: ModelSim/Questa Debugging
      13. 

    13. ModelSim / Questa: Waveform Grouping
      14. 

    14. ModelSim / Questa: Saving Waveforms Between Cursors
      15. 

    15. ModelSim / Questa: Waveform Expanded Time
      16. 

    16. Knowledge Check 3: ModelSim/Questa - Debugging
      17. 

    17. Lab: ModelSim/Questa - Logic Error
      18. 

    18. Assessment: ModelSim/Questa - Debugging Topics
      19. 

    

    

    

    

    

    HDS: Team Use and File Management 6 Chapters
    

    This learning path covers how to administer HDS for team operation, how to analyze existing designs, how to generate documentation, and how to use 3rd party IP.
    

    

    

    1 HDS: Using Viewpoints to Aid Investigation and Understanding of Designs 9 Topics
    

      

    1. HDS: Visualizing Design Data with Viewpoints
      2. 

    2. HDS: Setting the Columns seen in Design Explorer Views
      3. 

    3. HDS: Obtaining Summary Information on Your Design
      4. 

    4. Knowledge Check 1: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
      5. 

    5. HDS: Using the Advanced Find in Design Explorer
      6. 

    6. HDS: Using the Available Design Reports
      7. 

    7. Knowledge Check 2: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
      8. 

    8. Lab: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
      9. 

    9. Assessment: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
      10. 

    

    

    

    2 HDS: Setting up HDS Properties and Resources 8 Topics
    

      

    1. HDS: Defining the Available Resources
      2. 

    2. HDS: Declaring User Variables
      3. 

    3. Knowledge Check 1: HDS - Setting up HDS Properties and Resources
      4. 

    4. HDS: Defining Default Code Generation Preferences
      5. 

    5. HDS: User Defined Templates
      6. 

    6. Knowledge Check 2: HDS - Setting up HDS Properties and Resources
      7. 

    7. Lab: HDS - Setting up HDS Properties and Resources
      8. 

    8. Assessment: HDS - Setting up HDS Properties and Resources
      9. 

    

    

    

    3 HDS: IP and Vendor Flows 17 Topics
    

      

    1. HDS: How to Use IP Blocks within HDL Designer Designs
      2. 

    2. HDS: ModuleWare IP
      3. 

    3. HDS: Setting ModuleWare Instance Properties in Block Diagrams
      4. 

    4. Knowledge Check 1: HDS - IP and Vendor Flows
      5. 

    5. Lab: HDS ModuleWare Lab
      6. 

    6. HDS: Introduction to Using Vendor IP Flows
      7. 

    7. HDS: Xilinx CoreGen Flow
      8. 

    8. HDS: Xilinx Vivado Flow
      9. 

    9. HDS: Xilinx Vivado Flow Example
      10. 

    10. HDS: Altera MegaWizard Flow
      11. 

    11. Knowledge Check 2: HDS - IP and Vendor Flows
      12. 

    12. Lab: HDS Vendor Lab
      13. 

    13. HDS: How to Add a Gate Level Netlist into HDS
      14. 

    14. HDS: Verifying Gate Level Simulation Results
      15. 

    15. Knowledge Check 3: HDS - IP and Vendor Flows
      16. 

    16. Lab: HDS Gate Level Lab
      17. 

    17. Assessment: HDS - IP and Vendor Flows
      18. 

    

    

    
Discover

    4 HDS: Adding and Visualizing Existing Designs 9 Topics
    

      

    1. HDS: Design Reuse Part 1
      2. 

    2. HDS: Design Reuse Part 2
      3. 

    3. Knowledge Check 1: HDS - Adding and Visualizing Existing Designs
      4. 

    4. HDS: Visualization Versus Entry
      5. 

    5. HDS: Visualizing a Text File
      6. 

    6. HDS: Converting a Visualized File to a Graphics File
      7. 

    7. Knowledge Check 2: HDS - Adding and Visualizing Existing Designs
      8. 

    8. Lab: HDS  - Adding and Visualizing Existing Designs
      9. 

    9. Assessment: HDS - Adding and Visualizing Existing Designs
      10. 

    

    

    

    5 HDS: Introduction to Team Design 9 Topics
    

      

    1. HDS: Team Requirements
      2. 

    2. HDS: Defining Team Resources
      3. 

    3. Knowledge Check 1: HDS - Introduction to Team Design
      4. 

    4. HDS: Differences Between Team and User Preferences
      5. 

    5. HDS: Differences Between Team and User Templates and Tasks
      6. 

    6. HDS: Setting Team Version Management
      7. 

    7. Knowledge Check 2: HDS - Introduction to Team Design
      8. 

    8. Lab: HDS - Introduction to Team Design
      9. 

    9. Assessment: HDS - Introduction to Team Design
      10. 

    

    

    

    6 HDS: Producing Design Documentation 11 Topics
    

      

    1. HDS: Advantages and Limitations of OLE to Export Diagrams
      2. 

    2. HDS: OLE When Using the Drag Bar and Panels
      3. 

    3. HDS: How to Register and Use OLE Documentation Tools
      4. 

    4. HDS: Documenting Diagrams without OLE
      5. 

    5. Knowledge Check 1: HDS - Producing Design Documentation
      6. 

    6. Lab: HDS - Creating Documentation
      7. 

    7. HDS: Invoking HTML Creation
      8. 

    8. HDS: HTML Options and Settings Explained
      9. 

    9. Knowledge Check 2: HDS - Producing Design Documentation
      10. 

    10. Lab: HDS - Producing Design Documentation
      11. 

    11. Assessment: HDS - Producing Design Documentation
      12. 

    

    

    

    

    

    SystemVerilog UVM 8 Chapters
    

    In this learning path you will learn how to use the Universal Verification Methodology (UVM) to create reusable verification environments.
    

    

    

    1 UVM Overview 21 Topics
    

      

    1. UVM Glossary and OOP Review
      2. 

    2. UVM Methodology
      3. 

    3. UVM What UVM Provides
      4. 

    4. Knowledge Check 1: UVM Overview
      5. 

    5. UVM Topology and Agent
      6. 

    6. UVM Class Hierarchy
      7. 

    7. UVM Phases
      8. 

    8. Knowledge Check 2: UVM Overview
      9. 

    9. UVM Hello World Example
      10. 

    10. UVM Example: Transactions and Driver
      11. 

    11. UVM Example: Agent, Environment and Test Class
      12. 

    12. UVM Example: Running a Test
      13. 

    13. Knowledge Check 3: UVM Overview
      14. 

    14. UVM Configuration Class
      15. 

    15. UVM Factory
      16. 

    16. UVM Messaging
      17. 

    17. UVM Controlling Verbosity
      18. 

    18. UVM Debugging and Documentation
      19. 

    19. Knowledge Check 4: UVM Overview
      20. 

    20. Lab: First Look at SystemVerilog UVM
      21. 

    21. Assessment: UVM Overview
      22. 

    

    

    
Discover

    2 UVM Transactions and Sequences 14 Topics
    

      

    1. UVM Stimulus Introduction
      2. 

    2. UVM Transaction Coding Style
      3. 

    3. UVM Transaction Methods
      4. 

    4. Knowledge Check 1: UVM Transactions and Sequences
      5. 

    5. UVM do_copy and do_compare Methods
      6. 

    6. UVM convert2string and Other Do Methods
      7. 

    7. UVM Extended Transaction Classes and Guidelines
      8. 

    8. Knowledge Check 2: UVM Transactions and Sequences
      9. 

    9. UVM Sequences Introduction
      10. 

    10. UVM Test, Sequence, and Driver Handshake
      11. 

    11. UVM Sequences Summary
      12. 

    12. Knowledge Check 3: UVM Transactions and Sequences
      13. 

    13. Lab: UVM Transactions and Sequences
      14. 

    14. Assessment: UVM Transactions and Sequences
      15. 

    

    

    

    3 UVM Drivers and Sequencers 6 Topics
    

      

    1. UVM TLM Communication
      2. 

    2. UVM Drivers and Sequencers
      3. 

    3. UVM Interfaces and Emulation
      4. 

    4. Knowledge Check 1: UVM Drivers and Sequencers
      5. 

    5. Lab: UVM Sequencers and Drivers
      6. 

    6. Assessment: UVM Drivers and Sequencers
      7. 

    

    

    

    4 UVM Monitors and Agents 8 Topics
    

      

    1. UVM Monitors Introduction
      2. 

    2. UVM TLM Analysis Ports
      3. 

    3. UVM Monitor Example
      4. 

    4. UVM Agents Introduction
      5. 

    5. UVM Agents Example
      6. 

    6. Knowledge Check: UVM Monitors and Agents
      7. 

    7. Lab: UVM Monitors and Agents
      8. 

    8. Assessment: UVM Monitors and Agents
      9. 

    

    

    

    5 UVM Coverage Collectors 5 Topics
    

      

    1. UVM Coverage Collector Introduction
      2. 

    2. UVM Coverage Collector Example
      3. 

    3. Knowledge Check: UVM Coverage Collectors
      4. 

    4. Lab: UVM Coverage Collector
      5. 

    5. Assessment: UVM Coverage Collectors
      6. 

    

    

    

    6 UVM Scoreboards and Environments 8 Topics
    

      

    1. UVM Scoreboards Introduction
      2. 

    2. UVM Scoreboards Internals
      3. 

    3. UVM Scoreboards Hierarchical Example
      4. 

    4. UVM Scoreboards Flat Example
      5. 

    5. UVM Environments
      6. 

    6. Knowledge Check 1: UVM Scoreboards and Environments
      7. 

    7. Lab: UVM Scoreboards
      8. 

    8. Assessment: UVM Scoreboards
      9. 

    

    

    

    7 UVM Configuration and Factory 12 Topics
    

      

    1. UVM Configuration Introduction
      2. 

    2. UVM Configuration HDL to Test Example
      3. 

    3. UVM Configuration Objects
      4. 

    4. UVM  Configuration Test to Environment Example
      5. 

    5. Knowledge Check 1: UVM Configuration
      6. 

    6. UVM Configuration Agent to Monitor Example
      7. 

    7. UVM Configuration Sequences, Arrays and Debug
      8. 

    8. UVM Factory Introduction
      9. 

    9. UVM Factory Override Examples
      10. 

    10. Knowledge Check 2: UVM Configuration and Factory
      11. 

    11. Lab: UVM Configuration and Factory
      12. 

    12. Assessment: UVM Configuration and Factory
      13. 

    

    

    

    8 UVM Tests and Complex Sequences 13 Topics
    

      

    1. UVM Tests - Architecture
      2. 

    2. UVM Tests - Controlling the Run Phase
      3. 

    3. UVM Tests - Finding Sequencer Handles
      4. 

    4. UVM Complex Sequences - Single Protocol
      5. 

    5. Knowledge Check 1: UVM Tests and Complex Sequences
      6. 

    6. UVM Complex Sequences - Multiple Protocols
      7. 

    7. UVM Complex Sequences - Driver Synchronization
      8. 

    8. UVM Complex Sequences - Arbitration Overview
      9. 

    9. UVM Complex Sequences - Arbitration Algorithms
      10. 

    10. UVM Complex Sequences - Parallel and Layered Sequences
      11. 

    11. Knowledge Check 2: UVM Tests and Complex Sequences
      12. 

    12. Lab: UVM Tests and Virtual Sequences
      13. 

    13. Assessment: UVM Tests and Complex Sequences
      14. 

    

    

    

    

    

    Mastering Questa 12 Chapters
    

    This learning path helps you master Questa’s advanced functional verification environment in order to manage your tests and debug verification bugs.
    

    

    
Discover

    1 Mastering Questa Learning Path Overview 1 Topic
    

      

    1. Learning Path Overview
      2. 

    

    

    

    2 Verification Plan 15 Topics
    

      

    1. Questa: Verification Motivations and Process
      2. 

    2. Questa: Verification Plan Components
      3. 

    3. Knowledge Check 1: Verification Plan
      4. 

    4. Questa: Verification Management Tasks
      5. 

    5. Questa: Unified Coverage Database (UCDB)
      6. 

    6. Knowledge Check 2: Verification Plan
      7. 

    7. Questa:  Verification Management Flow
      8. 

    8. Questa: Creating a Verification Plan
      9. 

    9. Questa: Verification Plan Contents
      10. 

    10. Knowledge Check 3: Verification Plan
      11. 

    11. Questa: Export and Import a Verification Plan
      12. 

    12. Questa: Merging Verification Plan with Test Data
      13. 

    13. Knowledge Check 4: Verification Plan
      14. 

    14. Lab: The Verification Plan
      15. 

    15. Assessment: Verification Plan
      16. 

    

    

    

    3 Code Coverage 15 Topics
    

      

    1. Questa: Purpose and Benefits of Code Coverage
      2. 

    2. Questa: Types of Code Coverage
      3. 

    3. Knowledge Check 1: Code Coverage
      4. 

    4. Questa: Invoking Code Coverage
      5. 

    5. Questa: Code Coverage Analysis Windows
      6. 

    6. Knowledge Check 2: Code Coverage
      7. 

    7. Questa: Managing Coverage Exclusions
      8. 

    8. Questa: Reporting Coverage
      9. 

    9. Knowledge Check 3: Code Coverage
      10. 

    10. Lab: Performing Code Coverage
      11. 

    11. Questa: Saving Coverage Data (UCDB)
      12. 

    12. Questa: Managing Coverage Data
      13. 

    13. Knowledge Check 4: Code Coverage
      14. 

    14. Lab: Analyzing Code Coverage Results
      15. 

    15. Assessment: Code Coverage
      16. 

    

    

    

    4 Functional Coverage 9 Topics
    

      

    1. Questa: What is Functional Coverage?
      2. 

    2. Questa: How to Implement Functional Coverage?
      3. 

    3. Knowledge Check 1: Functional Coverage
      4. 

    4. Questa: Functional Coverage Plan
      5. 

    5. Questa: Filtering and Sampling Coverage
      6. 

    6. Questa: Functional Coverage in the GUI
      7. 

    7. Knowledge Check 2: Functional Verification
      8. 

    8. Lab: Functional Coverage
      9. 

    9. Assessment: Functional Coverage
      10. 

    

    

    
Discover

    5 Test Tracking 11 Topics
    

      

    1. Questa: Creating a Test Environment
      2. 

    2. Questa: Storing Attributes in the UCDB
      3. 

    3. Questa: Coverage View Mode
      4. 

    4. Knowledge Check 1: Test Tracking
      5. 

    5. Questa: Post-Simulation Analysis
      6. 

    6. Questa: Optimizing Regression Runs
      7. 

    7. Questa: Verification Analysis
      8. 

    8. Questa: Generating HTML Coverage Reports
      9. 

    9. Knowledge Check 2: Test Tracking
      10. 

    10. Lab: Test Tracking
      11. 

    11. Assessment: Test Tracking
      12. 

    

    

    

    6 SV Class Debugging 23 Topics
    

      

    1. Questa: Enabling Debugging for SV Classes
      2. 

    2. Questa: Questa Class Nomenclature
      3. 

    3. Questa: describe and examine Commands
      4. 

    4. Questa: Class Tree, Graph and Instances Windows
      5. 

    5. Knowledge Check 1: SV Class Debugging
      6. 

    6. Questa: Watch, Locals and Call Stack Windows
      7. 

    7. Questa: Viewing Class instances in the Wave Window
      8. 

    8. Questa: Finding Information about Your Classes
      9. 

    9. Knowledge Check 2: SV Class Debugging
      10. 

    10. Questa: User-Defined Radices
      11. 

    11. Questa: Memory Windows
      12. 

    12. Questa: Processes and Locals Windows
      13. 

    13. Knowledge Check 3: SV Class Debugging
      14. 

    14. Questa: Waveform Expanded Time
      15. 

    15. Questa: Tracing Readers and Drivers
      16. 

    16. Questa: Message Viewer window
      17. 

    17. Questa: Debugging Macros and the Call Command
      18. 

    18. Knowledge Check 4: SV Class Debugging
      19. 

    19. Questa: UVM-Aware Debug
      20. 

    20. Questa: Transaction Streams
      21. 

    21. Knowledge Check 5: SV Class Debugging
      22. 

    22. Lab: SystemVerilog Debugging
      23. 

    23. Assessment: SV Class Debugging
      24. 

    

    

    

    7 Performance 12 Topics
    

      

    1. Questa: What is vopt?
      2. 

    2. Questa: Optimization Flows
      3. 

    3. Questa: Preserving Visibility
      4. 

    4. Questa: Optimization of Parameters and Generics
      5. 

    5. Questa: Preserving VPI/PLI Visibility
      6. 

    6. Knowledge Check 1: Performance
      7. 

    7. Questa: Gate Level Optimization
      8. 

    8. Questa: vopt with Compiled SDF
      9. 

    9. Questa: The PDU Flow
      10. 

    10. Knowledge Check 2: Performance
      11. 

    11. Lab: Performance
      12. 

    12. Assessment: Performance
      13. 

    

    

    

    8 Debugging SystemVerilog Assertions 11 Topics
    

      

    1. Questa: Assertion-Based Verification
      2. 

    2. Questa: Assertions Window
      3. 

    3. Questa: Configure Assertions
      4. 

    4. Knowledge Check 1: Debugging SystemVerilog Assertions
      5. 

    5. Lab: Assertions Window
      6. 

    6. Questa: Assertions in the Wave Window
      7. 

    7. Questa: Assertion Thread Viewer Window
      8. 

    8. Questa: Usage of SV Bind Construct with Assertions
      9. 

    9. Knowledge Check 2: Debugging SystemVerilog Assertions
      10. 

    10. Lab: Debugging SystemVerilog Assertions
      11. 

    11. Assessment: Debugging SystemVerilog Assertions
      12. 

    

    

    

    9 Constrained Random Verification 7 Topics
    

      

    1. Questa: Randomization
      2. 

    2. Questa: Constraint Random Coding Guidelines
      3. 

    3. Questa: Constraint Solvers
      4. 

    4. Questa: Debugging Randomization Failures
      5. 

    5. Knowledge Check 1: Constrained Random Verification
      6. 

    6. Lab: Debugging a Failure in the Constraint Solver
      7. 

    7. Assessment: Constrained Random Verification
      8. 

    

    

    

    10 Performance Profiling 7 Topics
    

      

    1. Questa: Performance Profiling
      2. 

    2. Questa: Viewing Profiler Results
      3. 

    3. Knowledge Check 1: Performance Profiling
      4. 

    4. Questa: Memory Allocation Profiler
      5. 

    5. Questa: Capacity Analysis
      6. 

    6. Knowledge Check 2: Performance Profiling
      7. 

    7. Assessment: Performance Profiling
      8. 

    

    

    

    11 Transactions 6 Topics
    

      

    1. Questa: What is a Transaction?
      2. 

    2. Questa: Transaction Recording Flow
      3. 

    3. Questa: Viewing Related Transactions in the Wave Window
      4. 

    4. Knowledge Check 1: Transactions
      5. 

    5. Lab: Transaction Recording and Viewing
      6. 

    6. Assessment: Transactions
      7. 

    

    

    

    12 Using DPI 9 Topics
    

      

    1. Direct Programming Interface Introduction
      2. 

    2. Direct Programming Interface Importing C Routines
      3. 

    3. Direct Programming Interface Debugging with Questa
      4. 

    4. Lab: Introduction to DPI-C
      5. 

    5. Direct Programming Interface Models With Storage
      6. 

    6. Direct Programming Interface C Calling SystemVerilog
      7. 

    7. Knowledge Check: Using DPI
      8. 

    8. Lab: C Testbench
      9. 

    9. Assessment: Using DPI
      10. 

    

    

    

    

    

    HDS: Design Checker 4 Chapters
    

    This learning path supports users writing rtl code.  It helps them implement their company design guidelines as a rule set that can be tested by Design Checker.
    

    

    

    1 HDS: Introduction to DesignChecker 8 Topics
    

      

    1. HDS: Introducing Static Design Checking
      2. 

    2. HDS: Overview of DesignCheck Process
      3. 

    3. Knowledge Check 1: HDS - Introduction to DesignChecker
      4. 

    4. HDS: Overview of Running DesignChecker
      5. 

    5. HDS: DesignChecker Windows
      6. 

    6. Knowledge Check  2: HDS - Introduction to DesignChecker
      7. 

    7. Lab: HDS - Introduction to DesignChecker
      8. 

    8. Assessment: HDS - Introduction to DesignChecker
      9. 

    

    

    

    2 HDS: Understanding Rulesets and Policies 13 Topics
    

      

    1. HDS: Base Rules
      2. 

    2. HDS: Base Rule Parameters and Reference Guide
      3. 

    3. Knowledge Check 1: HDS - Understanding Rulesets and Policies
      4. 

    4. HDS: Building a Ruleset
      5. 

    5. HDS: Built-in Rulesets
      6. 

    6. HDS: Design Quality Metric
      7. 

    7. Knowledge Check 2: HDS - Understanding Rulesets and Policies
      8. 

    8. Lab: HDS - DC Ruleset Creation
      9. 

    9. HDS: Creating a Policy
      10. 

    10. HDS: Using Policies
      11. 

    11. Knowledge Check 3: HDS - Understanding Rulesets and Policies
      12. 

    12. Lab: HDS - DC Policy Creation
      13. 

    13. Assessment: HDS - Understanding Rulesets and Policies
      14. 

    

    

    

    3 HDS: Invoking and using DesignChecker in HDS 6 Topics
    

      

    1. HDS: How to See DesignChecker in HDS
      2. 

    2. Knowledge Check 1: HDS - Invoking and using DesignChecker in HDS
      3. 

    3. HDS: Invoking DesignChecker from HDS
      4. 

    4. Knowledge Check 2: HDS - Invoking and using DesignChecker in HDS
      5. 

    5. Lab: HDS - Invoking and using DesignChecker in HDS
      6. 

    6. Assessment: HDS - Invoking and using DesignChecker in HDS
      7. 

    

    

    
Discover

    4 HDS: Analyzing DesignChecker Results 12 Topics
    

      

    1. HDS: The Results Tab
      2. 

    2. HDS: Results Summary Pane
      3. 

    3. HDS: Tracing Errors to Design Source Views
      4. 

    4. Knowledge Check 1: HDS - Analyzing DesignChecker Results
      5. 

    5. Lab: HDS - Analyzing Results
      6. 

    6. HDS: How to Sort and Filter Results
      7. 

    7. HDS: Exporting of Results
      8. 

    8. HDS: Using DC to Analyze Quality of a Design
      9. 

    9. Knowledge Check 2: HDS - Analyzing DesignChecker Results
      10. 

    10. Lab: HDS - Exporting and Organizing Results
      11. 

    11. Lab: HDS - Working with Results
      12. 

    12. Assessment: HDS - Analyzing DesignChecker Results
      13. 

    

    

    

    

    

    UVM Framework 7 Chapters
    

    Learn how to quickly build sophisticated UVM testbenches with UVM Framework, a class library and code generator, part of the Questa? Verification Solution.
    

    

    

    1 UVM Framework Learning Path Overview 1 Topic
    

      

    1. Learning Path Overview
      2. 

    

    

    
Discover

    2 UVM Framework: Introduction 4 Topics
    

      

    1. UVM Framework: Introduction
      2. 

    2. UVM Framework: Design Under Test
      3. 

    3. UVM Framework: Plan Stimulus and Checks
      4. 

    4. Assessment: UVM Framework Introduction
      5. 

    

    

    

    3 UVM Framework: Create Interface 5 Topics
    

      

    1. UVM Framework: Describe the Input Protocol Interface
      2. 

    2. UVM Framework: Generate the Input Protocol Interface
      3. 

    3. UVM Framework: Create the Output Protocol Interface
      4. 

    4. Lab: UVM Framework: Create Interface
      5. 

    5. Assessment: UVM Framework: Create Interface
      6. 

    

    

    

    4 UVM Framework: Create Environment 3 Topics
    

      

    1. UVM Framework: Describe the Environment
      2. 

    2. UVM Framework: Generate the Environment
      3. 

    3. Assessment: UVM Framework: Create Environment
      4. 

    

    

    

    5 UVM Framework: Create Bench 4 Topics
    

      

    1. UVM Framework: Bench Description
      2. 

    2. UVM Framework: Bench Generation
      3. 

    3. Lab: UVM Framework: Create Bench
      4. 

    4. Assessment: UVM Framework: Create Bench
      5. 

    

    

    

    6 UVM Framework: Complete the Bench 10 Topics
    

      

    1. UVM Framework:  Simulate the Out of the Box Bench
      2. 

    2. Lab: Out of the Box Simulation
      3. 

    3. UVM Framework: Connect the DUT and Bench
      4. 

    4. Lab: Connect the DUT and Bench
      5. 

    5. UVM Framework: Drive and Monitor Input Transactions
      6. 

    6. UVM Framework: Drive and Monitor Output Transactions
      7. 

    7. Lab: Drive and Monitor Transactions
      8. 

    8. UVM Framework: Predict the Results
      9. 

    9. Lab: Predict the Results
      10. 

    10. Assessment: UVM Framework: Complete the Bench
      11. 

    

    

    

    7 UVM Framework: Start Verification 4 Topics
    

      

    1. UVM Framework: Create a New Test and Transaction
      2. 

    2. UVM Framework: Configuration and Sequences
      3. 

    3. Lab: Start Verification of DUT
      4. 

    4. Assessment: Start Verification
      5. 

    

    

    

    

    

    Visualizer 5 Chapters
    

    In this learning path you will learn how to use the Visualizer Debug Environment to verify your design.
    

    

    
Discover

    1 Visualizer Learning Path Overview 1 Topic
    

      

    1. Learning Path Overview
      2. 

    

    

    
Discover

    2 Chapter 1 - Introduction to Visualizer 5 Topics
    

      

    1. Visualizer: What Is the Visualizer and Why Use It?
      2. 

    2. Visualizer: Typical Usage Flows
      3. 

    3. Visualizer: Getting Help
      4. 

    4. Lab 1: Introduction to Visualizer
      5. 

    5. Assessment Introduction to Visualizer
      6. 

    

    

    

    3 Chapter 2 - Visualizer GUI 18 Topics
    

      

    1. Visualizer: Overview of GUI Operation
      2. 

    2. Visualizer: Design Window
      3. 

    3. Visualizer: Design Exploration with the Advanced Search
      4. 

    4. Knowledge Check 1: Visualizer GUI
      5. 

    5. Visualizer: Source Code Debug
      6. 

    6. Visualizer: Variables Window
      7. 

    7. Visualizer: Adding Signals to the Wave Window
      8. 

    8. Knowledge Check 2: Visualizer GUI
      9. 

    9. Visualizer: Wave Window - Part 1
      10. 

    10. Visualizer: Wave Window - Part 2
      11. 

    11. Visualizer: Tracing Drivers and Recievers
      12. 

    12. Visualizer: X Tracing
      13. 

    13. Knowledge Check 3: Visualizer GUI
      14. 

    14. Visualizer: Memory Window and Its Breakpoints
      15. 

    15. Visualizer: FSM Window
      16. 

    16. Knowledge Check 4: Visualizer GUI
      17. 

    17. Lab 2: Visualizer GUI
      18. 

    18. Assessment: Visualizer GUI
      19. 

    

    

    

    4 Chapter 3 - Visualizer Commands 4 Topics
    

      

    1. Visualizer: visualizer command
      2. 

    2. Visualizer: qwave2vcd and vcd2qwave Commands
      3. 

    3. Visualizer: viswave command
      4. 

    4. Assessment: Visualizer Commands
      5. 

    

    

    

    5 Chapter 4 - Debugging UVM Testbench 12 Topics
    

      

    1. Visualizer: UVM Testbench Window
      2. 

    2. Visualizer: UVM Testbench in Schematic and Watch Windows
      3. 

    3. Visualizer: Class Debug
      4. 

    4. Knowledge Check 1: UVM Testbench
      5. 

    5. Lab 3: UVM Testbench Exploration
      6. 

    6. Visualizer: UVM Transactions Streams
      7. 

    7. Lab 4: UVM Transaction Streams
      8. 

    8. Visualizer: Assertions Window
      9. 

    9. Visualizer: Assertion Thread Viewer Window
      10. 

    10. Knowledge Check 2: UVM Testbench
      11. 

    11. Lab 5: Assertions
      12. 

    12. Assessment: Debugging UVM Testbench
      13. 

    

    

    

    

    

    Questa Clock Domain Crossing (CDC) 2 Chapters
    

    Learn about clock domain crossing (CDC) design and verification and how to use Questa CDC to verify paths between asynchronous clock domains.
    

    

    
Discover

    1 Basic CDC Verification 25 Topics
    

      

    1. Questa CDC Introduction: CDC Challenges
      2. 

    2. Questa CDC Introduction: CDC Verification
      3. 

    3. Questa CDC: CDC Methodology - Part 1
      4. 

    4. Questa CDC: CDC Methodology - Part 2
      5. 

    5. Questa CDC: CDC Methodology - Part 3
      6. 

    6. Knowledge Check 1: CDC Overview
      7. 

    7. Questa CDC Setup: Understanding CDC Process and Design Compilation
      8. 

    8. Questa CDC Setup: Tcl Commands
      9. 

    9. Knowledge Check 2: CDC Overview
      10. 

    10. Questa CDC Setup: Clock Report
      11. 

    11. Questa CDC Setup: Clock Signals and Clock Grouping
      12. 

    12. Knowledge Check 3: CDC Overview
      13. 

    13. Questa CDC Setup: Resets and Port Domains
      14. 

    14. Knowledge Check 4: CDC Overview
      15. 

    15. Questa CDC Debug
      16. 

    16. Questa CDC: Synchronizer Flows for DFF, DMUX and Handshake Schemes
      17. 

    17. Questa CDC: Synchronizer Flow for FIFO Schemes
      18. 

    18. Knowledge Check 5: CDC Overview
      19. 

    19. Questa CDC: Reconvergence Schemes and Synchronizer Reporting
      20. 

    20. Knowledge Check 6: CDC Overview
      21. 

    21. Questa CDC: Status Method - Part 1
      22. 

    22. Questa CDC: Status Method - Part 2
      23. 

    23. Questa CDC: Status Method - Part 3
      24. 

    24. Knowledge Check 7: CDC Overview
      25. 

    25. Assessment: CDC Overview
      26. 

    

    

    

    

    

    UVM Intermediate 5 Chapters
    

    Create a UVM Register Layer description of hardware registers and memories, integrate into a UVM testbench, and verify your design with methods and sequences.
    

    

    

    1 UVM Intermediate Learning Path Overview 1 Topic
    

      

    1. Learning Path Overview
      2. 

    

    

    

    2 Register Layer Overview 4 Topics
    

      

    1. UVM Intermediate: Register Layer Introduction
      2. 

    2. UVM Intermediate: Register Block Concepts
      3. 

    3. UVM Intermediate: Register Layer Flow
      4. 

    4. Assessment:  Register Layer Overview
      5. 

    

    

    

    3 Register Description 5 Topics
    

      

    1. UVM Intermediate: Questa Register Assistant Flow
      2. 

    2. UVM Intermediate: Questa Register Assistant Inputs
      3. 

    3. UVM Intermediate: Questa Register Assistant Results
      4. 

    4. Lab: Register Description
      5. 

    5. Assessment: Register Description
      6. 

    

    

    

    4 Register Model Integration 6 Topics
    

      

    1. UVM Intermediate: Integration Overview
      2. 

    2. UVM Intermediate: Register Model Adapter
      3. 

    3. UVM Intermediate: Register Model Prediction
      4. 

    4. UVM Intermediate: Register Integration Example
      5. 

    5. Lab: Integrating Register Model
      6. 

    6. Assessment: Register Description
      7. 

    

    

    

    5 Applying the Register Model Layer 14 Topics
    

      

    1. UVM Intermediate: Apply Register Model Introduction
      2. 

    2. UVM Intermediate: Register Methods 1
      3. 

    3. UVM Intermediate: Register Methods 2
      4. 

    4. UVM Intermediate: Checking Registers
      5. 

    5. UVM Intermediate: Memories
      6. 

    6. UVM Intermediate: Introspection Methods
      7. 

    7. Knowledge Check 1: Apply Register Model
      8. 

    8. Lab: Apply the Register Model Layer
      9. 

    9. UVM Intermediate: Quirky Registers
      10. 

    10. UVM Intermediate: Functional Coverage
      11. 

    11. UVM Intermediate: Predefined Sequences
      12. 

    12. Knowledge Check 2: Apply Register Model
      13. 

    13. Lab: Quirky Registers
      14. 

    14. Assessment: Apply Register Model
      15. 

    

    

    

    

    

    UVM Framework QVIP Integration 7 Chapters
    

    Learn how to build a UVM testbench for an IP core using UVM Framework and Questa Verification IP (QVIP).
    

    

    
Discover

    1 Introduction to UVM Framework QVIP Integration 1 Topic
    

      

    1. Introduction to UVMF and QVIP
      2. 

    

    

    

    2 Creating the DUT 3 Topics
    

      

    1. Generating the DUT
      2. 

    2. Lab: Creating the DUT
      3. 

    3. Assessment: Creating the DUT
      4. 

    

    

    

    3 Creating the SVVA Testbench 3 Topics
    

      

    1. Creating the Testbench Project
      2. 

    2. Lab: Creating SVVA Testbench
      3. 

    3. Assessment: Creating SVVA Testbench
      4. 

    

    

    

    4 Generating the QVIP Interface 3 Topics
    

      

    1. Creating the QVIP Environment
      2. 

    2. Lab: Creating the QVIP Environment
      3. 

    3. Assessment: Generating the QVIP Interface
      4. 

    

    

    

    5 Generating the UVMF Testbench 3 Topics
    

      

    1. Generating the UVMF Testbench
      2. 

    2. Lab: Generating the UVMF Testbench
      3. 

    3. Assessment: Generating the UVMF Testbench
      4. 

    

    

    

    6 Importing the UVMF Testbench 3 Topics
    

      

    1. Importing the Generated UVMF Code Into a SVVA Project
      2. 

    2. Lab: Importing the UVMF Testbench
      3. 

    3. Assessment: Importing the UVMF Testbench
      4. 

    

    

    

    7 Completing the Testbench 3 Topics
    

      

    1. Completing & Simulating the UVMF Testbench
      2. 

    2. Lab: Completing the Testbench
      3. 

    3. Assessment: Completing the Testbench
      4. 

    

    

    

    

    

    Questa SIM SystemC 2 Chapters
    

    In this learning path you will receive an overview of SystemC and learn how to simulate SystemC designs in Questa.
    

    

    

    1 Introduction to SystemC 10 Topics
    

      

    1. Questa SIM SystemC: Introduction to C++
      2. 

    2. Questa SIM SystemC: Introduction to SystemC
      3. 

    3. Questa SIM SystemC: SystemC Basic Contructs
      4. 

    4. Knowledge Check 1: Introduction to SystemC
      5. 

    5. Questa SIM SystemC: SystemC Design Hierarchy
      6. 

    6. Questa SIM SystemC: SystemC Data Types
      7. 

    7. Questa SIM SystemC: SystemC Time
      8. 

    8. Knowledge Check 2: Introduction to SystemC
      9. 

    9. Lab 1: SystemC Hello World 
      10. 

    10. Assessment: Introduction to SystemC
      11. 

    

    

    

    2 SystemC in Questa SIM 6 Topics
    

      

    1. Questa SIM SystemC: Questa SIM SystemC General Flow
      2. 

    2. Questa SIM SystemC: Mixed HDL Support
      3. 

    3. Questa SIM SystemC: SystemC Different Flows
      4. 

    4. Lab 2: SystemC Shared Library Flow
      5. 

    5. Lab 3: SystemC Archived Models
      6. 

    6. Assessment: SystemC in Questa SIM
      7. 

    

    

    

    

    

    

    

    

    

    

    

    Discover Edition Training Chapters
    


    

    

    

    

    SystemVerilog Arrays, Structures, and Packages
    

    Learn about various types of arrays in SystemVerilog. This includes fixed and dynamic arrays, queues and associative arrays.
    

    

    

    SystemVerilog Arrays, Structures, and Packages 18 Topics
    

      

    1. SystemVerilog - Vectors and Arrays
      2. 

    2. SystemVerilog Array - Assignment and Comparison
      3. 

    3. SystemVerilog - Array Literals
      4. 

    4. Knowledge Check 1: SystemVerilog Arrays, Structures, and Packages
      5. 

    5. SystemVerilog - Dynamic Arrays
      6. 

    6. SystemVerilog - Strings
      7. 

    7. SystemVerilog - Queues
      8. 

    8. Knowledge Check 2: SystemVerilog Arrays, Structures, and Packages
      9. 

    9. SystemVerilog - Associative Arrays
      10. 

    10. SystemVerilog - Array Methods
      11. 

    11. SystemVerilog - Advanced Array Methods
      12. 

    12. Knowledge Check 3: SystemVerilog Arrays, Structures, and Packages
      13. 

    13. SystemVerilog - Structures
      14. 

    14. SystemVerilog - Packages
      15. 

    15. SystemVerilog - Package Import
      16. 

    16. Knowledge Check 4: SystemVerilog Arrays, Structures, and Packages
      17. 

    17. Lab: SystemVerilog Arrays, Structures, and Packages
      18. 

    18. Assessment: SystemVerilog Arrays, Structures, and Packages
      19. 

    

    

    

    

    

    Stimulus Optimization with inFact
    

    Learn about stimulus generation process and how to import existing UVM testbench into inFact-PSS environment.
    

    

    

    Stimulus Optimization with inFact 2 Topics
    

      

    1. Reference: Stimulus Optimization with inFact
      2. 

    2. Lab: Stimulus Optimization with inFact
      3. 

    

    

    

    

    

    Regression Optimization with inFact
    

    Learn about how to run regressions with inFact-PSS.
    

    

    

    Regression Optimization with inFact 2 Topics
    

      

    1. Reference: Regression Optimization with inFact
      2. 

    2. Lab: Regression Optimization with inFact
      3. 

    

    

    

    

    

    Coverage Goal Optimization with inFact
    

    Learn how to generate coverage goals using inFact PSS coverage generator.
    

    

    

    Coverage Goal Optimization with inFact 2 Topics
    

      

    1. Reference: Coverage Goal Optimization with inFact
      2. 

    2. Lab: Coverage Goal Optimization with inFact
      3. 

    

    

    

    

    

    Scenario Generation Optimization with inFact and PSS
    

    Learn about how to create scenarions with portable stimulus with InFact-PSS.
    

    

    

    Scenario Generation Optimization with inFact and PSS 2 Topics
    

      

    1. Reference: Scenario Generation Optimization with inFact and PSS
      2. 

    2. Lab: Scenario Generation Optimization with inFact and PSS
      3. 

    

    

    

    

    

    SystemVerilog Basic OOP
    

    This chapter introduces the basic concepts and operations in SystemVerilog OOP
    

    

    

    SystemVerilog Basic OOP 17 Topics
    

      

    1. SystemVerilog Introduction to Object Oriented Programming
      2. 

    2. SystemVerilog Introduction to Classes
      3. 

    3. SystemVerilog Questa Sim OOP Debug
      4. 

    4. SystemVerilog Constructors
      5. 

    5. Knowledge Check 1: SystemVerilog Basic OOP
      6. 

    6. SystemVerilog Handles and Objects 1
      7. 

    7. SystemVerilog Handles and Objects 2
      8. 

    8. SystemVerilog Shallow Object Copy
      9. 

    9. SystemVerilog Deep Object Copy
      10. 

    10. SystemVerilog Cloning Objects
      11. 

    11. Knowledge Check 2: SystemVerilog Basic OOP
      12. 

    12. SystemVerilog Class Declaration Details
      13. 

    13. SystemVerilog Static Properties and Methods
      14. 

    14. SystemVerilog Virtual Interfaces
      15. 

    15. Knowledge Check 3: SystemVerilog Basic OOP
      16. 

    16. Lab: SystemVerilog Basic OOP
      17. 

    17. Assessment: SystemVerilog Basic OOP
      18. 

    

    

    

    

    

    ModelSim/Questa HDL Simulation Learning Path Overview
    

    The storyboard document in this chapter provides an overview of the entire learning path.
    

    

    

    ModelSim/Questa HDL Simulation Learning Path Overview 1 Topics
    

      

    1. Learning Path Overview
      2. 

    

    

    

    

    

    ModelSim/Questa Introduction to Simulation
    

    This chapter provides an overview of simulation process. You will learn about the features of  QuestaSim and ModelSim and how to use Help and Documentation.
    

    

    

    ModelSim/Questa Introduction to Simulation 11 Topics
    

      

    1. ModelSim/Questa: Simulation in the Digital Design Flow
      2. 

    2. ModelSim/Questa: Simulation Process
      3. 

    3. Knowledge Check 1: ModelSim/Questa Introduction to Simulation
      4. 

    4. ModelSim/Questa: Overview of Features and Supported Industry Standards
      5. 

    5. ModelSim/Questa: Modes of Operation
      6. 

    6. ModelSim/Questa: Overview of Debugging Capabilities
      7. 

    7. Knowledge Check 2: ModelSim/Questa Introduction to Simulation
      8. 

    8. ModelSim/Questa: Getting Help
      9. 

    9. Knowledge Check 3: ModelSim/Questa Introduction to Simulation
      10. 

    10. Lab: ModelSim/Questa Documentation and Help
      11. 

    11. Assessment: ModelSim/Questa Introduction to Simulation
      12. 

    

    

    

    

    

    HDS: Design Entry Common Features
    

    You will learn about the features that are common to all, or the majority, of design entry tools within HDL Designer
    

    

    

    HDS: Design Entry Common Features 15 Topics
    

      

    1. HDS: Opening New or Existing Design Units
      2. 

    2. HDS: Bottom Up Design Flow
      3. 

    3. HDS: Top Down Design Flow
      4. 

    4. HDS: How to Save the Design
      5. 

    5. Knowledge Check 1: HDS Common Features
      6. 

    6. Lab: HDS Opening and Closing Designs
      7. 

    7. HDS: Adding Comments to Design Entry Tools
      8. 

    8. HDS: Defining the Page Setup for Viewing and Printing
      9. 

    9. HDS: Setting Package Preferences
      10. 

    10. HDS: Setting Preferences for the Design Tools
      11. 

    11. HDS: Using the Diagram Browser
      12. 

    12. HDS: How to Generate HDL Code from Graphics
      13. 

    13. Knowledge Check 2: HDS Common Features
      14. 

    14. Lab: HDS Preferences
      15. 

    15. Assessment: HDS Common Features
      16. 

    

    

    

    

    

    SystemVerilog Randomization
    

    Learn about random testing methodology and SystemVerilog constrained random testing
    

    

    

    SystemVerilog Randomization 19 Topics
    

      

    1. SystemVerilog Class-Based Randomization
      2. 

    2. SystemVerilog Randomization Example
      3. 

    3. SystemVerilog Constraint Solver
      4. 

    4. SystemVerilog Membership, Distribution, and Unique Constraints
      5. 

    5. SystemVerilog Implication Constraint
      6. 

    6. Knowledge Check 1: SystemVerilog Randomization
      7. 

    7. SystemVerilog Randomizing Arrays
      8. 

    8. SystemVerilog Randomizing Aggregate Types
      9. 

    9. SystemVerilog Random Distribution and Probability
      10. 

    10. SystemVerilog Constraint Inheritance and In-Line Constraints
      11. 

    11. SystemVerilog Soft Constraints
      12. 

    12. Knowledge Check 2: SystemVerilog Randomization
      13. 

    13. SystemVerilog Randomization Setup and Cleanup
      14. 

    14. SystemVerilog Random Cyclic Variables
      15. 

    15. SystemVerilog Disabling Randomization
      16. 

    16. SystemVerilog Randomization Issues and Alternatives
      17. 

    17. Knowledge Check 3: SystemVerilog Randomization
      18. 

    18. Lab: SystemVerilog Randomization
      19. 

    19. Assessment: SystemVerilog Randomization
      20. 

    

    

    

    

    

    ModelSim/Questa Tcl/TK Overview
    

    This chapter provides a brief overview to the TCL/Tk language, and shows how it can be  used within ModeSim or QuestaSim.
    

    

    

    ModelSim/Questa Tcl/TK Overview 10 Topics
    

      

    1. ModelSim / Questa: Why Use Tcl/Tk?
      2. 

    2. ModelSim / Questa: Tcl Overview
      3. 

    3. ModelSim / Questa: Tcl Syntax
      4. 

    4. ModelSim / Questa: Using vsim Commands in Tcl Scripts
      5. 

    5. ModelSim / Questa: Simple Simulation Scripts
      6. 

    6. Knowledge Check 1: ModelSim/Questa - Tcl/Tk Overview
      7. 

    7. ModelSim / Questa: Tk Widgets and Custom GUI Buttons
      8. 

    8. Knowledge Check 2: ModelSim/Questa - Tcl/Tk Overview
      9. 

    9. Lab: ModelSim/Questa - Using Scripts and Tk Widgets  in Simulation
      10. 

    10. Assessment: ModelSim/Questa - TCL/TK Overview
      11. 

    

    

    

    

    

    HDS: Adding and Visualizing Existing Designs
    

    Learn how to import existing HDL text designs into an HDL Project. Graphical analysis of the text file, and  conversion into a Graphical source are supported.
    

    

    

    HDS: Adding and Visualizing Existing Designs 9 Topics
    

      

    1. HDS: Design Reuse Part 1
      2. 

    2. HDS: Design Reuse Part 2
      3. 

    3. Knowledge Check 1: HDS - Adding and Visualizing Existing Designs
      4. 

    4. HDS: Visualization Versus Entry
      5. 

    5. HDS: Visualizing a Text File
      6. 

    6. HDS: Converting a Visualized File to a Graphics File
      7. 

    7. Knowledge Check 2: HDS - Adding and Visualizing Existing Designs
      8. 

    8. Lab: HDS  - Adding and Visualizing Existing Designs
      9. 

    9. Assessment: HDS - Adding and Visualizing Existing Designs
      10. 

    

    

    

    

    

    UVM Transactions and Sequences
    

    Learn how to create stimulus using UVM transactions and sequences.
    

    

    

    UVM Transactions and Sequences 14 Topics
    

      

    1. UVM Stimulus Introduction
      2. 

    2. UVM Transaction Coding Style
      3. 

    3. UVM Transaction Methods
      4. 

    4. Knowledge Check 1: UVM Transactions and Sequences
      5. 

    5. UVM do_copy and do_compare Methods
      6. 

    6. UVM convert2string and Other Do Methods
      7. 

    7. UVM Extended Transaction Classes and Guidelines
      8. 

    8. Knowledge Check 2: UVM Transactions and Sequences
      9. 

    9. UVM Sequences Introduction
      10. 

    10. UVM Test, Sequence, and Driver Handshake
      11. 

    11. UVM Sequences Summary
      12. 

    12. Knowledge Check 3: UVM Transactions and Sequences
      13. 

    13. Lab: UVM Transactions and Sequences
      14. 

    14. Assessment: UVM Transactions and Sequences
      15. 

    

    

    

    

    

    Mastering Questa Learning Path Overview
    

    The storyboard document in this chapter provides an overview of the entire Learning Path.
    

    

    

    Mastering Questa Learning Path Overview 1 Topics
    

      

    1. Learning Path Overview
      2. 

    

    

    

    

    

    Test Tracking
    

    This chaper explains how to create a test environment, analyze post-simulation run,  merge a test plan with test runs and how to generate HTML coverage reports.
    

    

    

    Test Tracking 11 Topics
    

      

    1. Questa: Creating a Test Environment
      2. 

    2. Questa: Storing Attributes in the UCDB
      3. 

    3. Questa: Coverage View Mode
      4. 

    4. Knowledge Check 1: Test Tracking
      5. 

    5. Questa: Post-Simulation Analysis
      6. 

    6. Questa: Optimizing Regression Runs
      7. 

    7. Questa: Verification Analysis
      8. 

    8. Questa: Generating HTML Coverage Reports
      9. 

    9. Knowledge Check 2: Test Tracking
      10. 

    10. Lab: Test Tracking
      11. 

    11. Assessment: Test Tracking
      12. 

    

    

    

    

    

    HDS: Analyzing DesignChecker Results
    

    This chapter explains how to manipulate and export DesignChecker results, how to analyze Design Quality and how to make use of Exclusions.
    

    

    

    HDS: Analyzing DesignChecker Results 12 Topics
    

      

    1. HDS: The Results Tab
      2. 

    2. HDS: Results Summary Pane
      3. 

    3. HDS: Tracing Errors to Design Source Views
      4. 

    4. Knowledge Check 1: HDS - Analyzing DesignChecker Results
      5. 

    5. Lab: HDS - Analyzing Results
      6. 

    6. HDS: How to Sort and Filter Results
      7. 

    7. HDS: Exporting of Results
      8. 

    8. HDS: Using DC to Analyze Quality of a Design
      9. 

    9. Knowledge Check 2: HDS - Analyzing DesignChecker Results
      10. 

    10. Lab: HDS - Exporting and Organizing Results
      11. 

    11. Lab: HDS - Working with Results
      12. 

    12. Assessment: HDS - Analyzing DesignChecker Results
      13. 

    

    

    

    

    

    UVM Framework: Introduction
    

    This chapter explains the benefits of UVM Framework, describes the Design Under Test, and introduces the UVM Framework flow.
    

    

    

    UVM Framework: Introduction 4 Topics
    

      

    1. UVM Framework: Introduction
      2. 

    2. UVM Framework: Design Under Test
      3. 

    3. UVM Framework: Plan Stimulus and Checks
      4. 

    4. Assessment: UVM Framework Introduction
      5. 

    

    

    

    

    

    Visualizer Learning Path Overview
    

    The storyboard document in this chapter provides an overview of the entire learning path.
    

    

    

    Visualizer Learning Path Overview 1 Topics
    

      

    1. Learning Path Overview
      2. 

    

    

    

    

    

    Chapter 1 - Introduction to Visualizer
    

    This chapter provides an overview of the Visualizer. You will learn about the Visualizer typical usage flows and how to use help and documentation.
    

    

    

    Chapter 1 - Introduction to Visualizer 5 Topics
    

      

    1. Visualizer: What Is the Visualizer and Why Use It?
      2. 

    2. Visualizer: Typical Usage Flows
      3. 

    3. Visualizer: Getting Help
      4. 

    4. Lab 1: Introduction to Visualizer
      5. 

    5. Assessment Introduction to Visualizer
      6. 

    

    

    

    

    

    Basic CDC Verification
    

    This chapter provides an understanding of the basic CDC verification process. You will learn how to setup and run Questa CDC and how to analyze CDC results.
    

    

    

    Basic CDC Verification 25 Topics
    

      

    1. Questa CDC Introduction: CDC Challenges
      2. 

    2. Questa CDC Introduction: CDC Verification
      3. 

    3. Questa CDC: CDC Methodology - Part 1
      4. 

    4. Questa CDC: CDC Methodology - Part 2
      5. 

    5. Questa CDC: CDC Methodology - Part 3
      6. 

    6. Knowledge Check 1: CDC Overview
      7. 

    7. Questa CDC Setup: Understanding CDC Process and Design Compilation
      8. 

    8. Questa CDC Setup: Tcl Commands
      9. 

    9. Knowledge Check 2: CDC Overview
      10. 

    10. Questa CDC Setup: Clock Report
      11. 

    11. Questa CDC Setup: Clock Signals and Clock Grouping
      12. 

    12. Knowledge Check 3: CDC Overview
      13. 

    13. Questa CDC Setup: Resets and Port Domains
      14. 

    14. Knowledge Check 4: CDC Overview
      15. 

    15. Questa CDC Debug
      16. 

    16. Questa CDC: Synchronizer Flows for DFF, DMUX and Handshake Schemes
      17. 

    17. Questa CDC: Synchronizer Flow for FIFO Schemes
      18. 

    18. Knowledge Check 5: CDC Overview
      19. 

    19. Questa CDC: Reconvergence Schemes and Synchronizer Reporting
      20. 

    20. Knowledge Check 6: CDC Overview
      21. 

    21. Questa CDC: Status Method - Part 1
      22. 

    22. Questa CDC: Status Method - Part 2
      23. 

    23. Questa CDC: Status Method - Part 3
      24. 

    24. Knowledge Check 7: CDC Overview
      25. 

    25. Assessment: CDC Overview
      26. 

    

    

    

    

    

    Introduction to UVM Framework QVIP Integration
    

    UVM Framework QVIP Integration
    

    

    

    Introduction to UVM Framework QVIP Integration 1 Topics
    

      

    1. Introduction to UVMF and QVIP
      2. 

    

    

    

    

    

    

    

    

    

    


    

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