Verification Horizons
Current Issue
Volume 16, Issue 2
In This Issue
Formal Is The “New Normal” — Deploy These FV Apps In Your Next Project
Formal verification is now pervasive in many chip design verification projects. Key to this widespread adoption is the availability of automated “apps” that makes it easy to deploy Formal in... View Journal Article
Understanding the SVA Engine Using the Fork-Join Model
SVA (SystemVerilog Assertions) is a powerful short-handed assertion language with many constructs; it is built as an integral part of SystemVerilog but with a specific syntax and sets of rules. Unlike a... View Journal Article
Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC Using Portable Stimulus
Over the past decades number of gates on IC’s and complexity of designs have increased rapidly which has caused various challenges in verifying circuits. Today’s IP, FPGA, and SoC engineers... View Journal Article
PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application
PCI Express® (PCIe®) is a dominant technology for hardware applications requiring high-speed connectivity between networking, storage, FPGA, and GPGPU boards to servers and desktop systems. It is... View Journal Article
Extending SoC Design Verification Methods for RISC-V Processor DV
As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established... View Journal Article
Addressing VHDL Verification Challenges with OSVVM
Most people don't think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can... View Journal Article
Effective Validation Method of Safety Mechanism Compliant with ISO 26262
The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified... View Journal Article
Volume 16, Issue 1
In This Issue
Verify Thy Verifyer
As with any large framework, there is more than one way to get things done in UVM. As a technical lead, one wants to establish a set of coding guidelines/best practices and ensure that his/her team members... View Journal Article
AI-Based Sequence Detection
NLP is basically a vast field of research broadly used for determining speech or text written in communication languages. NLP grew out of the field of linguistics and has succeeded above expectations so... View Journal Article
Using Questa? SLEC to Speed Up Verification of Multiple HDL Outputs
The verification team at Codasip decided to employ the Questa® SLEC app in the process of ensuring that each HDL representation is the same, expecting that it will significantly reduce total verification... View Journal Article
An Open Data Management Tool for Design and Verification
The Big Data technology has evolved to handle both volume and velocity of data, currently being generated by the chip design and verification activities. However, we feel that the core challenge of effective... View Journal Article
Detecting Security Vulnerabilities in a RISC-V? Based System-on-Chip
Commonly employed security verification techniques, which include manual design and code review, formal verification, and simulation-based functional verification are important as part of a larger verification... View Journal Article
Formal Verification of RISC-V? Processors
Functional verification of processors has been a known challenge, but with the advent of open-source RISC-V® a new wave of computing has ushered. Not only universities, but several big corporations... View Journal Article
Volume 15, Issue 3
In This Issue
Deadlock Prevention Made Easy with Formal Verification
You are about to go into a planning meeting for a new project when you get a call from one of your company's Customer Advocate Managers: a product that you worked on just started shipping in volume,... View Journal Article
Designing A Portable Stimulus Reuse Strategy
Creating sufficient tests to verify today's complex designs is a key verification challenge, and this challenge is present from IP block-level verification all the way to SoC validation. The...
View Journal Article
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Today's complex designs include multiple asynchronous clocks and the signals crossing between asynchronous clock-domains may result in functional errors. When a signal from one asynchronous clock-domain... View Journal Article
Exercising State Machines with Command Sequences
Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key... View Journal Article
Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
There is no doubt that computers have changed our lives forever. Still, as much as computers outperform humans at complex tasks such as solving complex mathematical equations in almost zero time, they may... View Journal Article
Volume 15, Issue 2
SystemC FMU for Verification of Advanced Driver Assistance Systems
An integrated framework to simulate electronic systems (including digital and analog devices) with the mechanical parts of a heterogeneous automotive system is presented. The electronic system, consisting... View Journal Article
Creating Tests the PSS Way in SystemVerilog
Portable Stimulus is one of the latest hot topics in the verification space. Mentor, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test... View Journal Article
Formal Bug Hunting with “River Fishing” Techniques
Formal verification has been used successfully to verify today’s SoC designs. Traditional formal verification, which starts from time 0, is good for early design verification, but it is inefficient... View Journal Article
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Clock-Domain Crossing (CDC) issues are the second most common reason for silicon re-spins. Most modern day designs have more than one clock, many of which are asynchronous. Signals that pass between logic... View Journal Article
Auto-Generating Implementation-Level Sequences for PSS
The Portable Test and Stimulus Standard (PSS) v1.0a aims to help the user describe the high-level test intent and create code for any downstream verification platform. This article starts out with a quick... View Journal Article
UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs
The Mentor UVMF documentation and examples provided great direction on how to generate a UVMF framework from scratch via, in this case, Python scripting. And then, boom, in fairly short order and from an... View Journal Article
Volume 15, Issue 1
In This Issue
SystemC FMU for Verification of Advanced Driver Assistance Systems
An integrated framework to simulate electronic systems (including digital and analog devices) with the mechanical parts of a heterogeneous automotive system is presented. The electronic system, consisting... View Journal Article
Creating Tests the PSS Way in SystemVerilog
Portable Stimulus is one of the latest hot topics in the verification space. Mentor, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test... View Journal Article
Formal Bug Hunting with “River Fishing” Techniques
Formal verification has been used successfully to verify today’s SoC designs. Traditional formal verification, which starts from time 0, is good for early design verification, but it is inefficient... View Journal Article
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Clock-Domain Crossing (CDC) issues are the second most common reason for silicon re-spins. Most modern day designs have more than one clock, many of which are asynchronous. Signals that pass between logic... View Journal Article
Auto-Generating Implementation-Level Sequences for PSS
The Portable Test and Stimulus Standard (PSS) v1.0a aims to help the user describe the high-level test intent and create code for any downstream verification platform. This article starts out with a quick... View Journal Article
UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs
The Mentor UVMF documentation and examples provided great direction on how to generate a UVMF framework from scratch via, in this case, Python scripting. And then, boom, in fairly short order and from an... View Journal Article
Volume 14, Issue 3
In This Issue
FPGA Verification Challenges and Opportunities
There have been multiple studies on IC/ASIC functional verification trends published over the years.[1][2][3][4] However, there are no published studies specifically focused on Field-Programmable Gate... View Journal Article
Building a Better Virtual Sequence with Portable Stimulus
Good virtual sequences are challenging to create, and even more challenging to reuse in a way not explicitly intended by the original author. Portable stimulus can make creating virtual sequences easier,... View Journal Article
Simplifying Mixed-Signal Verification
Mixed-signal design is the art of taking real world analog information, such as light, touch, sound, vibration, pressure, or temperature, and bringing it into the digital world for processing. The growth... View Journal Article
A New Approach to Low-Power Verification: Power Aware Apps
As the low-power architecture is complex and the number of power-domains used in designs is high, selective reporting of a part of a design is needed. The lack of an industry standard in this regard has... View Journal Article
Volume 14, Issue 2
In This Issue
Comprehensive CDC Verification with Advanced Hierarchical Data Models
As CDC signals can lead to metastability, CDC metastability issues have become one of the leading causes of design re-spins. This trend has made CDC verification an even more critical step in the design... View Journal Article
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
At SoC level, verifying access to registers confirms that the processor byte order matches the interconnect implementation, and that the boot code properly configures the memory management unit (MMU) such... View Journal Article
It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
Just as functional verification uses coverage to determine completeness, the ISO standard defines a form of coverage for random hardware failures called diagnostic coverage, which represents the percentage... View Journal Article
Coverage Driven Verification of NVMe Using Questa? VIP (QVIP)
The key to functional coverage is to make an exhaustive verification plan containing coverpoints and crosses which are extracted from the protocol specification. View Journal Article
Part 2: PA Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
In Part II of the article, we conclude this discussion with a real example to analyze PA-Static results and reporting, as well as efficient debugging PA-Static anomalies. View Journal Article
Three Main Components to Look for in Your Emulation Platform
Hardware emulation has sufficient execution speed, full visibility capabilities and ease-of-use in model creation and model updates to span the entire range of needs throughout the life of the design development... View Journal Article
Complex Addressable Registers in Mission Critical Applications
In this article, we will discuss some complex registers that we have seen our customers use in mission-critical applications. View Journal Article
RTL Glitch Verification
Traditionally, engineers have verified that a design is safe from glitches with delay-annotated gate-level simulation. View Journal Article
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
RISC-V is a free-to-use and open ISA developed at the University of California, Berkeley, now officially supported by the RISC-V Foundation. View Journal Article
Volume 14, Issue 1
In This Issue
Make Your Constraints More Dynamic with Portable Stimulus
Accellera’s Portable Stimulus Standard (PSS) introduces some new constraint capabilities, in addition to supporting the capabilities that we’ve become familiar with in SystemVerilog. This article... View Journal Article
Configuring Memory Read Completions Sent by PCIe? QVIP
This article covers the various ways with which a completion can be returned and how these ways can be implemented in software. View Journal Article
SATA Specification 3.3 Gaps Filled by SATA QVIP
Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors... View Journal Article
Part I: Power Aware Static Verification—From Power Intent to Microarchitectural Checks of Low-Power Designs
The fundamental technique that a PA-Static checking tool enforces to verify a design statically involves ascertaining the compliance of the MV or PA rules with the power intent or UPF specifications and... View Journal Article
SVA Alternative for Complex Assertions
This article first explains the concepts, and then by example, how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding... View Journal Article
A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
A RISC-V based SoC can be configured into different implementations based on architectural or micro-architectural parameters. To address the verification challenge this poses, a hierarchical and configurable... View Journal Article
Volume 13, Issue 3
In This Issue
Parallel Debug: A Path to a Better Big Data Diaspora
This article describes a methodology—parallel debug—as well as a supporting Jenkins framework, enabled by the availability of massive processor and disc farms which are commonplace among chip... View Journal Article
Portable Stimulus Modeling in a High-Level Synthesis User’s Verification Flow
Portable Stimulus has become quite the buzz-word in the verification community in the last year or two, but like most ‘new’ concepts it has evolved from some already established tools and methodologies. View Journal Article
Smoothing the Path to Software-Driven Verification with Portable Stimulus
Verification and validation of the hardware/software boundary cannot reasonably be deferred until prototype bring-up in the lab, because software is so critical to the operation of today’s systems.... View Journal Article
Verification Planning with Questa? Verification Management
This article contains detailed steps to use this tracking process along with key features which can reduce the time in verification cycle to track the verification progress. View Journal Article
Converting Legacy USB IP to a Low Power USB IP
What it really takes to successfully achieve a low power design is design team know-how and a simulation tool that is geared towards low power implementation. This article captures how we use Mentor’s... View Journal Article
Understanding the UPF Power Domain and Domain Boundary
The Universal Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. View Journal Article
Automation and Reuse in RISC-V Verification Flow
The Open RISC-V Instruction Set Architecture (ISA) managed by the RISC-V foundation[1] and backed by an ever increasing number of the who’s who in the semiconductor and systems world, provides... View Journal Article
Emulation – A Job Management Strategy to Maximize Use
There are many reasons why hardware-based emulation is a “must have” for an effective verification flow. Increased complexity, protocols, embedded software, power and verification at the system... View Journal Article
RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success
Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level... View Journal Article
Formal Verification: Not Just for Control Paths
Proper interleaving of SystemVerilog helper constructs with protocol targeted assumptions defines a manageable state space and unlocks the promise of formal driven, full path verification for datapaths... View Journal Article
Volume 13, Issue 2
In This Issue
EDA Support for Functional Safety — How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
Functional safety is a major enabler of many of the current and upcoming automotive products and has been formalized by the ISO 26262 standard. View Journal Article
Step-by-step Tutorial for Connecting Questa? VIP into the Processor Verification Flow
This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification environments by QVIP Configurator and Questa® VIP (QVIP) components. View Journal Article
PA GLS: The Power Aware Gate-level Simulation
During GL-netlist PA-SIM, corruption will occur on the output ports and sequential logic of any detected gate-level cells. View Journal Article
Reset Verification in SoC Designs
In this article, we present the commonly occurring issues that are involved in reset tree verification and solutions to address them. View Journal Article
Debugging Inconclusive Assertions and a Case Study
In this article, we discuss the flow to debug inconclusive assertions and use an ECC design as an example to show a decomposition technique for handling inconclusive assertions. View Journal Article
Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus
This article shows how Accellera PSS can be used to develop generic test intent for generating memory traffic in an SoC, and how that generic test intent is targeted to a specific design. View Journal Article
Volume 13, Issue 1
In This Issue
UVM Tips and Tricks
This article will furnish several examples to improve the performance of the UVM testbench by applying different optimizing techniques to random access generation, configuration database, objection mechanism,... View Journal Article
Will Safety Critical Design Practices Improve First Silicon Success?
Perhaps one of the biggest challenges in design and verification today is identifying solutions to increase productivity to control engineering head count View Journal Article
A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products
The computers are fleeing their cages. Until recently, people interacted with computers in a virtual world of screens and mice. That world had many security risks but relatively few safety risks, mostly... View Journal Article
Bridging UVM to the Portable Stimulus Standard with Questa? inFact
While UVM is great in building testbenches and test scenarios/sequences, the primary objective of UVM was to build robust, reusable testbenches. View Journal Article
Automating Tests with Portable Stimulus from IP to SoC Level
Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. The bulk of this effort has focused on techniques that are most applicable... View Journal Article
Complementing Functional Verification Through the Use of Available Timing Information
Functional verification is often focused on verification of the logical functions of the design. An overlooked area closely related to functional verification is proper implementation of the logic. View Journal Article
Artifacts of Custom Checkers in Questa? Power Aware Dynamic Simulation
UPF provides a mechanism to separate the binding of such customized PA assertions from both functional SystemVerilog assertions (SVA) and the design. View Journal Article
Volume 12, Issue 3
How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology
With ever increasing design complexities, ASIC and SoC (system on chip) design verification has become the biggest challenge for design and verification engineers. Various Hardware Description Languages... View Journal Article
USB Type-C Verification: Challenges and Solution
The standard USB connector that we are most familiar with is USB Type-A. Even as the USB data interface moved from USB1 to USB2 and then to USB3, the connector has remained the same. It is a massive connector... View Journal Article
INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution
Automotive vehicles are not only fast moving, but also have various systems comprising a variety of advanced technologies. Increasing complexities of these systems need much more sophisticated components... View Journal Article
24 x 7 Productivity: Veloce? Enterprise Server App Does the Job
The way companies use hardware emulation has changed. Historically, emulators were used in a lab, at one location, executing one job at a time. Because of this, an emulator often sat idle. In this scenario,... View Journal Article
Power Aware Libraries: Standardization and Requirements for Questa? Power Aware
Multivoltage (MV) based power-ware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive... View Journal Article
Improving Performance and Verification of a System Through an Intelligent Testbench
The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step... View Journal Article
Volume 12, Issue 2
How Formal Techniques Can Keep Hackers from Driving You into a Ditch
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Simplifying HDCP Verification Using Questa? VIP
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Accelerating Networking Products to Market
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
The Advantage of Using Mentor Graphics for the Physical Verification of FPGAs in Accordance with an Aerospace DO254 Methodology Flow
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Extending UVM Verification Models for the Analysis of Fault Injection Simulations
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Saving Time and Improving Quality with a Specification to Realization Flow
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Volume 12, Issue 1
In This Issue
An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Increased Efficiency with Questa? VRM and Jenkins Continuous Integration
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Total Recall: What to Look for in a Memory Model Library
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Certus? Silicon Debug: Don't Prototype Without It
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Simplified UVM for FPGA Reliability: UVM for "Sufficient Elemental Analysis" in DO-254 Flows
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Complex Signal Processing Verification under DO-254 Constraints
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Simplifying Generation of DO-254 Compliant Verification Documents for AEH Devices
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
DO-254 Compliant UVM VIP Development
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Reusable Verification Framework
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
MIPI C-PHY?: Man of the Hour
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Nine Effective Features of NVMe? Questa? Verification IP to Help You Verify PCIe? Based SSD Storage
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
First Time Unit Testing Experience Report with SVUnit
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Volume 11, Issue 3
In This Issue
Memories Are Made Like This
Memory models have two main functions. The first is to store information in a data structure so that it can be written, retrieved and updated. The second is to provide a signal level interface which allows... View Journal Article
A New Stimulus Model for CPU Instruction Sets
Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure... View Journal Article
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However,... View Journal Article
QVIP Provides Thoroughness in Verification
The present day designs use standard interfaces for the connection and management of functional blocks in System on Chips (SoCs). These interface protocols are so complex that, creating in-house VIPs could... View Journal Article
Minimizing Constraints to Debug Vacuous Proofs
Most false positives (i.e. missing design bugs) during the practice of model checking on industrial designs can be reduced to the problem of a failing cover. Debugging the root cause of such a failing cover... View Journal Article
A Generic UVM Scoreboard
All UVM engineers employ scoreboarding for checking DUT/reference model behavior, but only few spend their time wisely by employing an existing scoreboard architecture. The main reason is that existing... View Journal Article
Hardware Emulation: Three Decades of Evolution—Part III
At the beginning of the third decade, circa 2005, system and chip engineers were developing evermore complex designs that mixed many interconnected blocks, embedded multicore processors, digital signal... View Journal Article
Volume 11, Issue 2
In This Issue
Verifying Airborne Electronics Hardware: Automating the Capture of Assertion Verification Results for DO-254
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
DO-254 Testing of High Speed FPGA Interfaces
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Formal and Assertion-Based Verification of MBIST MCPs
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Starting Formal Right from Formal Test Planning
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Reuse MATLAB Functions and Simulink Models in UVM Environments with Automatic SystemVerilog DPI Component Generation
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Intelligent Testbench Automation with UVM and Questa
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Unit Testing Your Way to a Reliable Testbench
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Hardware Emulation: Three Decades of Evolution – Part II
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Accelerating RTL Simulation Techniques
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Emulation Based Approach to ISO 26262 Compliant Processors Design
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Resolving the Limitations of a Traditional VIP for PHY Verification
This article focuses on Assertion-Based Verification (ABV) methodology and discusses automation techniques for capturing verification results to accelerate the verification process. View Journal Article
Volume 11, Issue 1
In This Issue
Does Design Size Influence First Silicon Success?
In this article, we present a few highlights from the 2014 Wilson Research Group Functional Verification Study that was commissioned by Mentor Graphics. One of the key takeaways from our study is that verification... View Journal Article
Successive Refinement: A Methodology for Incremental Specification of Power Intent
In this article, we present the UPF Successive Refinement methodology in detail. We explain how power management constraints can be specified for IP blocks to ensure correct usage in a power-managed system.... View Journal Article
PowerAware RTL Verification of USB 3.0 IPs
Mentor’s Questa PowerAware RTL verification methodology helps in defining multiple power architectures without changing the RTL by defining the power architecture in a power intent UPF file independent... View Journal Article
Hardware Emulation: Three Decades of Evolution
Let’s look closely at these three periods with special consideration to the characteristics of the hardware emulators and how they evolved. Let’s also take a look at what’s behind hardware... View Journal Article
Evolving the Use of Formal Model Checking in SoC Design Verification
Verification is widely accepted as the long pole in the project schedule and SoC design teams are tasked with verifying increasingly complex designs. View Journal Article
Small, Maintainable Tests
In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept... View Journal Article
Functional Coverage Development Tips: Do’s and Don’ts
This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios... View Journal Article
Volume 10, Issue 3
In This Issue
Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Fast Track to Productivity Using Questa Verification IP
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Cache Coherent Interface Verification IP
Learn about VIP master APIs that could be reused to generate stimulus on a cache coherent interface without worrying about accessing the cache model and other testbench objects. View Journal Article
Hey You, Design Engineer!
How design engineers can get verification engineers to stop complaining, and other advice. View Journal Article
Please! Can Someone Make UVM Easier to Use?
UVM unified many of the older methodologies and is a culmination of many years of work. But many of the practices of yester years crept in. Using some of those practices can cause needless complication... View Journal Article
Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
Handling resets on the fly in UVM environments can be accomplished if the testbench components are built with reset awareness as described in the article. View Journal Article
Increase Verification Productivity with Questa UVM debug
Questa UVM debug helped the TVS team channelize effort that was otherwise being unproductively spent in fixing verification environment issues towards more critical verification tasks like feature addition... View Journal Article
Volume 10, Issue 2
In This Issue
Stories of an AMS Verification Dude: Model Shmodel
Well here I am again. Last time I talked about putting stuff together, and when I mean stuff, it turned out that the digital folks handed me an RTL and the analog dudes gave me a SPICE netlist. View Journal Article
Increasing Verification Productivity Through Functional Coverage Management Automation
Functional coverage plays a very important role in verifying the completeness of a design. However customizing a coverage plan for different chips, users, specification versions, etc. is a very tedious... View Journal Article
Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components
SystemVerilog provides a way called weightage constraints using which, one can implement dynamism in today’s verification components. Support for normal implementation of weight-age constraints is... View Journal Article
UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment
Developing UVM-based testbenches from scratch is a time consuming and error-prone process. Engineers have to learn object oriented programming (OOP), a technique with which ASIC developers generally are... View Journal Article
Merging SystemVerilog Covergroups by Example
SystemVerilog has the concept of covergroups that can keep track of conditions observed during a simulation. View Journal Article
Is It Magic, or Ingenious People Working with Remarkably Advanced Technology?
My 16 year-old son just came downstairs to my office (I’m blessed to work from home) to reboot our home network router so that our television could connect to the internet. View Journal Article
Best Practices for FPGA and ASIC Development
This is an overview of best practices for FPGA or ASIC design, assuming a traditional waterfall development process. View Journal Article
Visualizer? Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!
Debugging these modern class-based testbenches has been painful for at least two reasons. First, they are designed and built using object-oriented coding styles, macros, dynamic transactions, phasing and... View Journal Article
MIPI LLI Verification using Questa Verification IP
This article describes how incorporating LLI Questa verification intellectual property (QVIP) can yield a host of benefits, including faster, more flexible verification and easier debugging. View Journal Article
Optimizing Emulator Utilization
Emulators, like Mentor Graphics Veloce®, are able to run designs in RTL orders of magnitude faster than logic simulators. View Journal Article
Volume 10, Issue 1
In This Issue
Don’t Forget the Little Things That Can Make Verification Easier
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Taming Power Aware Bugs with Questa
The internet revolution has changed the way we share content and the mobile revolution has boosted this phenomenon in terms of content creation & consumption. Moving forward, the Internet of Things... View Journal Article
Using Mentor Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged and tested. View Journal Article
Dealing With UVM and OVM Sequences
Because UVM/OVM are TLM-based, sequence and sequence items play vital roles and must be created in the most efficient way possible in order to reduce rework and simulation time, and to make the verification... View Journal Article
Portable VHDL Testbench Automation with Intelligent Testbench Automation
Questa inFact graph-based intelligent testbench automation provides just such a “bridge” for VHDL testbench environments. View Journal Article
Stories of an AMS Verification Dude: Putting Stuff Together
I don't know how this came about, but the other day I got hired to do something called AMS Verification. It seems that there is this chip design that combines digital and analog stuff, and I was asked... View Journal Article
Whether It's Fixing a Boiler, or Getting to Tapeout, It's Productivity that Matters
Being up against a tapeout deadline isn’t all that different from fixing a heating system before a winter storm hits. Although the stakes are different in these two scenarios, it’s ultimately... View Journal Article
Volume 9, Issue 1
Software-Driven Testing of AXI Bus in a Dual Core ARM System
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Caching in on Analysis
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
DDR SDRAM Bus Monitoring using Mentor Verification IP
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Simulation + Emulation = Verification Success
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Life Isn’t Fair, So Use Formal
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
AMS Verification for High Reliability and Safety Critical Applications
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Assertions Instead of FSMs/logic for Scoreboarding and Verification
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
Volume 15, Issue 2
In This Issue
