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Siemens EDA: Where Electronic Design Automation meets tomorrow.
White Papers and Case Studies
Using AWS cloud services for IC library characterization that is scalable, secure, and fast.
Siemens’ AMS Verification team and Amazon Web Services (AWS) have collaborated to provide users with a scalable, secure and cost-effective cloud characterization flow that enables users to leverage...
Optimizing HLS code for different FPGA platforms
Digital logic solutions developers have a range of platforms they can choose from to implement their solution. The choice of platform could be simply choosing between ASIC or FPGA depending upon the potential...
Multi-Layer Deep Data Performance Monitoring and Optimization
Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field,...
Tessent LogicBIST with Observation Scan Technology
Meeting the ISO 26262 requirements for high quality and long-term reliability mans implementing on-chip safety mechanisms with high defect coverage of IC logic. This paper describes Observation Scan Technology,...
Multicore system management
Based on pragmatic experience of helping customers through the decision-making process, this paper addresses the most frequently asked questions developers have when choosing how to control and manage a...
A novel processing platform for post tape out flows
As the computational requirements for post tape out (PTO) flows increase, computational tools need to scale as well. Using design hierarchy helps, but as the data is processed through the PTO flow, its...
Reduction of systematic defects with machine learning from design to fab
This paper presents machine learning and computational lithography methods to identify and eliminate yield limiting patterns in the design, improve the accuracy of mask generation with etch and resist modeling...
Mask process correction validation for multi-beam mask lithography
In this paper, we present a full cycle of MPC calibration and verification, using existing, proven mask processes in combination with a novel MBMW system.
Upcoming Webinars and Events
Eliminate Schematic Design Errors with Automated Verification
Detect critical design errors and eliminate design re-spins caused by schematic errors by automating the process of board-level verification.
Functional Safety: ISO 26262 Creating an Optimal Safety Architecture
In this session you will gain an understanding of the core challenges defining an optimal safety architecture.
Analog Mixed Signal (AMS) Flow using SCL 180nm PDK
This Webinar will explain more about the various steps involved in Analog Mixed Signal design flow. It demonstrates the schematic capture, Analog SPICE simulation and Mixed Signal simulations, Layout implementation...
The ABC of Formal Verification
This webinar focuses on property checking and the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage.
MEMS Digital Qualification - Predicting Yield During Initial Design
Learn how Siemens EDA Tanner MEMS solutions, SoftMEMS, OnScale, and MATLAB statistical analysis tools work together to predict actual device performance and yield of a MEMS device manufactured by SilTerra...
IESF 2020 conference program, now in its 20th year, will include events in Japan, Detroit, Germany and for the first time Portland, Oregon (as part of the EVS33 conference and with a particular focus on EV and AD).
IESF is the leading automotive conference on EE design trends and solutions. IESF Automotive 2020 focuses on four key areas: EE Architecture, Connectivity, Autonomous Driving, and Electrification.
Recent Blogs All Blogs
Why are UVM transactions built with uvm_sequence_item?Chris Spear
Article Roundup: Calibre nmLVS-Recon to streamline IC circuit verification,…Expert Insights
Article Roundup: Siemens raises Capital to full E/E design level, Why Go Cu…Expert Insights
Parallel Debug: A Path to a Better Big Data Diaspora
This article describes a methodology—parallel debug—as well as a supporting Jenkins framework, enabled by the availability of massive processor and disc farms which are commonplace among chip...
E-Cooling: Cooling Power Electronics at Room Level
E-Cooling, an engineering consultancy firm based in Germany, has expertise in the thermal design of Power Electronics, Transformers and Chokes at the component level or at room level where the computational...
Trials and Demos
On-Demand, Online, and Classroom Training
Capital On-Demand Training Library
Courses include interactive videos, written course materials, knowledge checks, and hands-on labs through the Mentor Graphics Virtual Lab platform. This platform utilizes a test environment where you can...
PADS Standard Plus On-Demand Training Library
This library will show you how to use PADS Standard Plus to design PCB boards. It contains learning paths for schematic and PCB design.
Functional Verification On-Demand Training Library
This library contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies.
|Apr 29, 2021 - Apr 30, 2021||Live online|
|Jul 26, 2021 - Jul 27, 2021||Live online|
This course is for verification engineers who are using UVM to code complex testbenches and stimulus for digital designs including registers. And have had some experience or training, but now need to know...
|Mar 15, 2021 - Mar 19, 2021||Shanghai, China|
Library Part Creation in the Xpedition Flow
The xDM Library Tools™ course will give you the skills necessary to create, protect, add to, and change the different data types in your Central Library.
|Feb 15, 2021 - Feb 16, 2021||Bangalore, India|
|Mar 04, 2021 - Mar 05, 2021||Shanghai, China|
|Jun 16, 2021 - Jun 16, 2021||Hsinchu City, Taiwan|
Calibre Advanced Topics: nmLVS Debug Case Studies
Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmLVS continues to be the pre-eminent tool for this task. Recent Calibre enhancements have...