Catapult® High-Level Synthesis
The industry’s leading High-Level Synthesis platform with proven quality of results and 25-50% reductions in verification cost.
The Catapult High-Level Synthesis (HLS) Platform empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level.
The Catapult High-Level Synthesis Platform empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level.
From these high-level descriptions, Catapult generates production-quality RTL. By speeding time to RTL and by automating the generation of bug free RTL, Catapult significantly reduces the time to verified RTL. The Catapult Platform pairs synthesis with the power of formal C property checking to find bugs early at the C/C++/SystemC level and to comprehensively verify source code before synthesis.
Catapult’s advanced power optimizations automatically provide significant reductions in dynamic power consumption. The highly-interactive Catapult workflow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for power, performance, and area.
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Key Features/Benefits
- Native SystemC and ANSI C++ synthesis
- Write 80% less code to save time and make debug easy
- Simulate 100-1000x faster for reduced verification time
- RTL optimized for power, performance, area, and RTL verification
- Tightly integrated formal C property checking for C based verification
"As Catapult earned our trust through predictable functional accuracy and high quality of result, we gained the needed confidence to assign bigger designs to the tool, resulting in even larger productivity gains."
Alexandre Cellier, STMicroelectronics
"Our microprocessor design teams are consistently innovating to increase overall performance and deliver industry-leading performance-per-watt. The fast, comprehensive verification which Calypto’s SLEC provides enhances this creative process, helping our design teams continue to meet the processing needs of our customers."
Nihar Mohapatra, AMD
"With the Catapult flow, RTL debug literally disappears. The C model is validated in its environment, and from there correct-byconstruction RTL is created. This reduces the verification effort dramatically."
Giuseppe Bonanno, STMicroelectronics
"We consider SLEC an important tool in our high-level design flow."
Osamu Tada, Renesas
Catapult HLS Platform
C/C++/SystemC Synthesis HLS
Lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production-quality RTL to dramatically shorten both design and verification in hardware design flows.
HLS Verification
HLS Verification with the Catapult Platform has three categories:
- Automatic/formal checking of users HLS targeted C++/SystemC code finding errors before synthesis.
- Simulation based verification comparing functionality of users C++/SystemC source with generated RTL including metrics such as coverage and assertions.
- Formal verification of equivalence of the users C++/SystemC code with the generated RTL from synthesis
Low-Power HLS
The industry’s first HLS tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult Low-Power provides a closed-loop optimization across power, performance and area to address the challenges of power-aware design.
