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    User2User MARLUG

    The Mentor User Conference
    Mid-Atlantic Region Local User Group

    Laurel, Maryland
    January 26, 2021

    U2U Logo
    Seminar

    Register Now

    Jan 26, 2021 Laurel, Maryland
    9:00 AM - 3:00 PM US/Eastern

    Overview

    Update on COVID-19:

    In an ongoing effort to protect our community, we have rescheduled the U2U Mid-Atlantic/MARLUG conference for January 26, 2021.

    The health and well-being of our Mentor family of customers, employees, and partners is our top priority. We are continuously monitoring the impact of COVID-19, evaluating all new developments, and determining measures to protect the health and safety of our communities in accordance with the guidance of international and national authorities.

    Please stay safe and watch this space for additional event details later this year.

     

    The U2U Mid-Atlantic Region Users Group (MARLUG) conference is a one-day event geared toward Electrical Engineers, ASIC/FPGA Engineers, PCB designers and Manufacturing Engineers that use or plan to use Mentor tools.

    Come network with your peers from companies across the region to learn about useful tips and tricks, as well as new product capabilities.

    Registration and breakfast will start at 8:00 am, with the opening keynote beginning at 9:00 am.  We will close out the day with a networking reception after the final session at 3:00 pm.

    U2U is always free to attend, but pre-registration is required. Space is limited so register today!

    What to Expect

    U2U MARLUG will have three tracks with topics delivered by Mentor customers and Mentor product experts who will be on hand to answer your questions about the tools, the engineering process, and solutions for your design challenges.

    Tracks 1 and 2: Printed Circuit Board Design and Simulation

    The PCB track has a wide range of topics, First, there will be a presentation on Valor NPI and how it is integrated with Xpedition with Xpedition PCB in Vx2.6. You will also see a customer presentation of a case study on Xpedition’s Rigid Flex functionality.  You will learn about Chiplets and how they are designed using the Xpedition Substrate Integrator tool, and a customer presentation on EDM library and how they plan on using it to handle multiple librarians at multiple sites across the country.

    The Simulation Track will feature topics based on the Mentor HyperLynx toolset.  Introduction to Power Aware with Hyperlynx, Case studies with the Hyperlynx Full Wave Solver, how to write scripts in Hyperlynx linesim and boardsim.

    Track 3: ASIC & FPGA: Advanced Functional Verification

    The verification track will focus on adoption of new methodologies to solve complex verification tasks while limiting the disruption of change. Users will present their experiences in adopting advanced simulations flows including regression management, test bench creation, advanced debug and simulation acceleration techniques. In addition to advanced simulation flows users will present how automatic formal methods can be used to solve complex verification tasks such as code coverage closure, Clock domain crossing verification, connectivity checking and automatic formal verification techniques.

    Who Should Attend

    Electronic design engineers and their managers interested in exploring innovative products and solutions that help engineers to solve design challenges in the increasingly complex worlds of board and chip design.

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    Keynote

    AJ Incorvaia

    AJ Incorvaia

    Senior Vice President,EBS
    Mentor, A Siemens Business

    A.J. Incorvaia is currently senior vice president of the Electronic Board Systems group at Mentor, A Siemens Business. AJ joined Mentor in October 2014 as the vice president and general manager of the company’s Board Systems Division. Prior to this he was vice president of the PCB and IC Packaging Group at Cadence Design Systems. During his sixteen years at Cadence AJ had held a number of positions, including vice president of Product Development for the PCB group, engineering group director and senior engineering manager. Prior to Cadence, AJ held software development and management positions at Viewlogic and Digital Equipment Corporation. He holds a B.S in Computer Science from the Rochester Institute of Technology, and an M.S in Computer Science and Software Engineering from George Mason University.

    Venue Information

    Johns Hopkins University Kossiakoff Center

    11100 Johns Hopkins Rd, Laurel, MD 20723
    Tel: (240) 228-5000
    Directions

    Registration & Breakfast will start at 8:00 AM with the first keynote starting at 9:00 AM.  The final session will approximately end at 3:00 PM followed by a closing session/networking reception.  This one-day conference is presented without conference fees but participants are responsible for their own travel expenses and accommodations.

    Hotel Recommendation

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    Homewood Suites Columbia/Laurel

    7531 Montpelier Road
    Laurel, Maryland, 20723
    TEL: +1-240-360-2725

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